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[209.132.180.67]) by mx.google.com with ESMTP id w16si22657512plk.568.2017.11.27.00.14.34; Mon, 27 Nov 2017 00:14:46 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751675AbdK0IMb (ORCPT + 78 others); Mon, 27 Nov 2017 03:12:31 -0500 Received: from david.siemens.de ([192.35.17.14]:44120 "EHLO david.siemens.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751311AbdK0IMK (ORCPT ); Mon, 27 Nov 2017 03:12:10 -0500 Received: from mail3.siemens.de (mail3.siemens.de [139.25.208.14]) by david.siemens.de (8.15.2/8.15.2) with ESMTPS id vAR8C2mC018957 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 27 Nov 2017 09:12:02 +0100 Received: from md1f2u6c.ww002.siemens.net ([167.87.32.153]) by mail3.siemens.de (8.15.2/8.15.2) with ESMTP id vAR8BtEd021016; Mon, 27 Nov 2017 09:12:01 +0100 From: Jan Kiszka To: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" Cc: x86@kernel.org, Linux Kernel Mailing List , jailhouse-dev@googlegroups.com Subject: [PATCH v2 11/12] x86/jailhouse: Wire up IOAPIC for legacy UART ports Date: Mon, 27 Nov 2017 09:11:53 +0100 Message-Id: <90d942dda9d48a8046e00bb3c1bb6757c83227be.1511770314.git.jan.kiszka@siemens.com> X-Mailer: git-send-email 2.12.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jan Kiszka The typical I/O interrupts in non-root cells are MSI-based. However, the platform UARTs do not support MSI. In order to run a non-root cell that shall be use one of them, we need to register the standard IOAPIC and set 1:1 routing for IRQ 3 and 4. If an IOAPIC is not available, the boot loader clears standard_ioapic in the setup data, and we skip the registration. If we should not be allowed to use one of those pins, Jailhouse will simply ignore our accesses. Signed-off-by: Jan Kiszka --- arch/x86/kernel/jailhouse.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c index c8ee638b6bce..8ff21e1534de 100644 --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -54,6 +55,15 @@ static unsigned long jailhouse_get_tsc(void) static void __init jailhouse_get_smp_config(unsigned int early) { + struct ioapic_domain_cfg ioapic_cfg = { + .type = IOAPIC_DOMAIN_STRICT, + .ops = &mp_ioapic_irqdomain_ops, + }; + struct mpc_intsrc mp_irq = { + .type = MP_INTSRC, + .irqtype = mp_INT, + .irqflag = MP_IRQPOL_ACTIVE_HIGH | MP_IRQTRIG_EDGE, + }; unsigned int cpu; if (x2apic_enabled()) { @@ -79,6 +89,17 @@ static void __init jailhouse_get_smp_config(unsigned int early) } smp_found_config = 1; + + if (setup_data.standard_ioapic) { + mp_register_ioapic(0, 0xfec00000, gsi_top, &ioapic_cfg); + + /* Register 1:1 mapping for legacy UART IRQs 3 and 4 */ + mp_irq.srcbusirq = mp_irq.dstirq = 3; + mp_save_irq(&mp_irq); + + mp_irq.srcbusirq = mp_irq.dstirq = 4; + mp_save_irq(&mp_irq); + } } static void jailhouse_no_restart(void) -- 2.12.3 From 1585222374605749738@xxx Mon Nov 27 12:31:04 +0000 2017 X-GM-THRID: 1585222374605749738 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread