Received: by 10.223.164.202 with SMTP id h10csp669500wrb; Thu, 30 Nov 2017 05:41:42 -0800 (PST) X-Google-Smtp-Source: AGs4zMb/RBBkjQa4Jzpud3pg4kuZUb7xWlpTiwluvZcjbZ9aKyc9FHmPuVRsDNeZtOf0z6ogPS01 X-Received: by 10.84.171.193 with SMTP id l59mr2614350plb.163.1512049302130; Thu, 30 Nov 2017 05:41:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1512049302; cv=none; d=google.com; s=arc-20160816; b=F5dL9ZiEP5xB0urlJEtn+YOfJ2S6yVUI3I2v6fCorlvgpbnJBycPGibiPiPcpDvFMn mXT3eIsuYgpnMz4Cun7FLcUsm6waAteLO5zCYUPFF/3TxmJBbJ0BKf++kTKVaWAQo438 7X38FqMPtt0xp6q/hjhs5m/47UxGQj22Qm0Godts9qAl0jwJpC/wbmlKuu+iTm1ZND7P 1qOAEC4uOBz1CcETneRMKvHnX3DyP81MIY3e6ZjQNO8M9l658OBwN4hygkNKUw0MEBUH 4PnSY4TZUtBhpyGBM0TR4zP1AG87k/5PNkKrj4m8lfwiSL2nms06aTdUQnHmBjP8A6/J Xx4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from :arc-authentication-results; bh=hN/AeG/70Zh1N9Nqro/yfioIUhWOEaOCjMxBlgV2jms=; b=hfJQxD1rXw2UfP3Hgba3XHYPO9JaCetNjuutwoOByLGQfkfRjlbipsocnX55zjl0wP 3LzVTprPAIly07UmBDnUz0LroVaMcVKmJzfaTUADmlhXE9ng0lSNf2/fv2BeQb12uY57 +JLXe7rEfMa7pqBNjavCqEoIMU5turIOeB1SzSGSjE3fiizXj3epQDicfH0zP82T9Rz5 B1+XqYr9bZ/+5ochwpMaErFylyOsHeyYOIX4mgupF2VUXhRxWO9xJTBAyXbE3DT4XbVl 7TSJTe748YEOUpYAx9oG5VWRvYStM9QR9dQ5VKaPtV+fydOSdY6MzzL/Wt4s4oKNSzoG reTg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 1si3103931plk.773.2017.11.30.05.41.28; Thu, 30 Nov 2017 05:41:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752563AbdK3NlC (ORCPT + 99 others); Thu, 30 Nov 2017 08:41:02 -0500 Received: from mail.free-electrons.com ([62.4.15.54]:33368 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751810AbdK3NlA (ORCPT ); Thu, 30 Nov 2017 08:41:00 -0500 Received: by mail.free-electrons.com (Postfix, from userid 110) id ECBB820869; Thu, 30 Nov 2017 14:40:58 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (242.171.71.37.rev.sfr.net [37.71.171.242]) by mail.free-electrons.com (Postfix) with ESMTPSA id C529620741; Thu, 30 Nov 2017 14:40:48 +0100 (CET) From: Gregory CLEMENT To: Stephen Boyd , Mike Turquette , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory CLEMENT , Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, Antoine Tenart , =?UTF-8?q?Miqu=C3=A8l=20Raynal?= , Nadav Haklai , Victor Gu , Marcin Wojtas , Wilson Ding , Hua Jing , Neta Zur Hershkovits Subject: [PATCH 0/3] Add DVFS support on CPU clock for Armada 37xx Date: Thu, 30 Nov 2017 14:40:26 +0100 Message-Id: <20171130134029.20751-1-gregory.clement@free-electrons.com> X-Mailer: git-send-email 2.15.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, This small series is needed to use DVFS on Armada 37xx. When DVFS is enabled the CPU clock setting is done using an other set of registers from the North Bridge Power Management block. The series adds the possibility to modify the CPU frequency using the associate load level matching the target frequency. However configuring the frequencies for each load is done by the cpufreq driver submitted in a separate series. Obviously having both series (cpufreq and clk) is needed to support DVFS on Armada 37xx, but there is no dependencies between the series (for building or at runtime). Thanks, Gregory Gregory CLEMENT (3): clk: mvebu: armada-37xx-periph: cosmetic changes clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks drivers/clk/mvebu/armada-37xx-periph.c | 310 +++++++++++++++++++++++++++++++-- 1 file changed, 293 insertions(+), 17 deletions(-) -- 2.15.0 From 1585214380342163749@xxx Mon Nov 27 10:24:00 +0000 2017 X-GM-THRID: 1584842506339346945 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread