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[209.132.180.67]) by mx.google.com with ESMTP id m2si4147411pll.139.2017.11.27.19.20.12; Mon, 27 Nov 2017 19:20:24 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=i6CZXa+J; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752500AbdK1DTh (ORCPT + 78 others); Mon, 27 Nov 2017 22:19:37 -0500 Received: from mail-vk0-f66.google.com ([209.85.213.66]:36781 "EHLO mail-vk0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751389AbdK1DTe (ORCPT ); Mon, 27 Nov 2017 22:19:34 -0500 Received: by mail-vk0-f66.google.com with SMTP id p144so18858669vkp.3; Mon, 27 Nov 2017 19:19:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=dOHq7SR5s83wcKrA1KEPO87JhdPoqbgdTo8RZg2ES9o=; b=i6CZXa+J4ReeD7UvwlQPiAEaT8+RQeI0xffNqQMyBWMKLlq/GP1IksZnWNHeoCeawO tpdlp+OBRI0RwOq5ZjvHVC31S59p2W2ax02jtjM8yvp01cK+YI1e3IN2kjM+L0H+uIb9 W0NDovL0je+po7AXVyYhCky7HQ7jACTaceKjbnpW3TYeZPbfwiXeVxW3zVl6c0Ptsk3G Jg4RIoCrjOHpYM2izo23I/Ms30r2g4NENzbKLyaqwUvm9x4P2HjnmB3u9qBJDVy+Xxck 8N4lYh2CuJ4UXjxDFHaQnnKTylnlcVMP7iJEpaZCDKMV2f0Gmp2u1atF+tvbGRBUDpb5 YxXg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=dOHq7SR5s83wcKrA1KEPO87JhdPoqbgdTo8RZg2ES9o=; b=N0rrsrO1m4zea9c3ffsYhQCmUjepjnuZXDln+4yaW+igvOUO5vZ8wyAUgqUPz/KblT +vWBeeUkiTu87UtcTI8XvieyF6SsJ4/StHo2YWbaa5Po9ebqcCDSTUSN3RScUbsAI+/z PXSC/OCjCf0HgTViNU+qUqEziN3IARqlt2EQUFjGdeAR9nleqQpRy0yYtD43qghmDtgw BFbvNLO6zucVmGTsMZ71D+Gg2MLwfQ4vC1FRKoKagETLtDSmITeWhA1WvVWjtukPqRyy 2vdRFvfSMJQWsbLO47HkDKyuHwf5HsSjAgwGEm1O1iWga6bd7baLmuH1KEfZY/hGVBnE JYqA== X-Gm-Message-State: AJaThX40GvJ2p+Fk8kMBkZtVjRkcabmfsfgh3pV/mH+A5/o3LwPZ0M9c lqQsm3ZzjDHhtER0vkLWr0y7T/F6p5EcChhvRL4= X-Received: by 10.31.157.213 with SMTP id g204mr8479103vke.130.1511839173037; Mon, 27 Nov 2017 19:19:33 -0800 (PST) MIME-Version: 1.0 Received: by 10.159.62.8 with HTTP; Mon, 27 Nov 2017 19:18:52 -0800 (PST) In-Reply-To: <20171127134232.q343uymer47zt74m@lakrids.cambridge.arm.com> References: <20a04f4a5b08dcec221e0c511e42ff3df711ae66.1511785528.git.green.hu@gmail.com> <20171127134232.q343uymer47zt74m@lakrids.cambridge.arm.com> From: Greentime Hu Date: Tue, 28 Nov 2017 11:18:52 +0800 Message-ID: Subject: Re: [PATCH v2 29/35] dt-bindings: nds32 CPU Bindings To: Mark Rutland Cc: Greentime , Linux Kernel Mailing List , Arnd Bergmann , linux-arch , Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring , netdev , Vincent Chen , DTML , Al Viro , David Howells , Will Deacon , Daniel Lezcano , linux-serial@vger.kernel.org, Vincent Chen , Rick Chen , Zong Li Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2017-11-27 21:42 GMT+08:00 Mark Rutland : > Him > > On Mon, Nov 27, 2017 at 08:28:16PM +0800, Greentime Hu wrote: >> From: Greentime Hu >> >> This patch adds nds32 CPU binding documents. >> >> Signed-off-by: Vincent Chen >> Signed-off-by: Rick Chen >> Signed-off-by: Zong Li >> Signed-off-by: Greentime Hu >> --- >> Documentation/devicetree/bindings/nds32/cpus.txt | 32 ++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/nds32/cpus.txt >> >> diff --git a/Documentation/devicetree/bindings/nds32/cpus.txt b/Documentation/devicetree/bindings/nds32/cpus.txt >> new file mode 100644 >> index 0000000..c302c89 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/nds32/cpus.txt >> @@ -0,0 +1,32 @@ >> +* Andestech Processor Binding >> + >> +This binding specifies what properties must be available in the device tree >> +representation of a Andestech Processor Core, which is the root node in the >> +tree. >> + >> +Required properties: >> + >> + - compatible: >> + Usage: required >> + Value type: >> + Definition: should be one of: >> + "andestech,n13" >> + "andestech,n15" >> + "andestech,d15" >> + "andestech,n10" >> + "andestech,d10" >> + "andestech,nds32v3" > > Are these specific parts, or architecture versions? > > I guess "andestech,nds32v3" is an architecture version, and the rest are > specific parts? Yes, nds32v3 is an architecture version and the rest are nds32v3 compatible processor's name. >> + - device_type >> + Usage: required >> + Value type: >> + Definition: must be "cpu" >> + - clock-frequency: Contains the clock frequency for CPU, in Hz. >> + >> +* Examples >> + >> +/ { >> + cpu { >> + device_type = "cpu"; >> + compatible = "andestech,n13", "andestech,nds32v3"; >> + }; > > This is missing the required clock-frequency property. > > There should be a /cpus node, with each CPU listed under that, to align > with the devicetree spec. Even if you never support SMP, there's no > reason to be different from other architectures. > > You should have something like: > > / { > cpus { > cpu { > device_type = "cpu"; > compatible = "andestech,n13"; > clock-frequency = <...>; > }; > }; > }; > > Thanks, > Mark. Thanks. I will modify it in the next version patch. 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