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[80.210.64.78]) by smtp.gmail.com with ESMTPSA id 19sm8506317wmn.15.2017.11.23.04.33.15 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Thu, 23 Nov 2017 04:33:15 -0800 (PST) Date: Thu, 23 Nov 2017 13:33:27 +0100 From: Christoffer Dall To: Alex =?iso-8859-1?Q?Benn=E9e?= Cc: julien.thierry@arm.com, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, Catalin Marinas , Will Deacon , open list Subject: Re: [PATCH v1 1/2] kvm: arm64: handle single-step during SError exceptions Message-ID: <20171123123327.GY28855@cbox> References: <20171123121134.11050-1-alex.bennee@linaro.org> <20171123121134.11050-2-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20171123121134.11050-2-alex.bennee@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 23, 2017 at 12:11:33PM +0000, Alex Benn�e wrote: > When an SError arrives during single-step it may be delivered before > the step completes. nit: this is not entirely accurate wording comparing with the ARM ARM, which says that the step would be completed, but you'll now have both a pending debug exception and a pending SError interrupt at the same time, and the architecture doesn't prevent the SError from being taken first. I can fix this up on commit though. > In that case the DBG_SPSR_SS bit will have flipped > as the instruction executed. After handling the abort in handle_exit() > we test to see if the bit is clear and we were single-stepping before > deciding if we need to exit to user space. > > Signed-off-by: Alex Benn�e Thanks! Reviewed-by: Christoffer Dall > --- > arch/arm64/kvm/handle_exit.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c > index 3e645ec9e751..3ba8c4a3bcff 100644 > --- a/arch/arm64/kvm/handle_exit.c > +++ b/arch/arm64/kvm/handle_exit.c > @@ -28,6 +28,7 @@ > #include > #include > #include > +#include > > #define CREATE_TRACE_POINTS > #include "trace.h" > @@ -250,7 +251,12 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, > return 1; > case ARM_EXCEPTION_EL1_SERROR: > kvm_inject_vabt(vcpu); > - return 1; > + /* We may still need to return for single-step */ > + if (!(*vcpu_cpsr(vcpu) & DBG_SPSR_SS) > + && kvm_arm_handle_step_debug(vcpu, run)) > + return 0; > + else > + return 1; > case ARM_EXCEPTION_TRAP: > return handle_trap_exceptions(vcpu, run); > case ARM_EXCEPTION_HYP_GONE: > -- > 2.15.0 > From 1584858871928204770@xxx Thu Nov 23 12:13:21 +0000 2017 X-GM-THRID: 1584858871928204770 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread