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[209.132.180.67]) by mx.google.com with ESMTP id g7si8618571pln.421.2017.11.20.05.33.24; Mon, 20 Nov 2017 05:33:34 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751242AbdKTNcr (ORCPT + 66 others); Mon, 20 Nov 2017 08:32:47 -0500 Received: from bastet.se.axis.com ([195.60.68.11]:39480 "EHLO bastet.se.axis.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751086AbdKTNcn (ORCPT ); Mon, 20 Nov 2017 08:32:43 -0500 Received: from localhost (localhost [127.0.0.1]) by bastet.se.axis.com (Postfix) with ESMTP id 2D3F6183BD; Mon, 20 Nov 2017 14:32:41 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at bastet.se.axis.com Received: from bastet.se.axis.com ([IPv6:::ffff:127.0.0.1]) by localhost (bastet.se.axis.com [::ffff:127.0.0.1]) (amavisd-new, port 10024) with LMTP id pkGLwxCBLhRC; Mon, 20 Nov 2017 14:32:40 +0100 (CET) Received: from boulder03.se.axis.com (boulder03.se.axis.com [10.0.8.17]) by bastet.se.axis.com (Postfix) with ESMTPS id 59035180E6; Mon, 20 Nov 2017 14:32:40 +0100 (CET) Received: from boulder03.se.axis.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 44E931E07F; Mon, 20 Nov 2017 14:32:40 +0100 (CET) Received: from boulder03.se.axis.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 38BFE1E07D; Mon, 20 Nov 2017 14:32:40 +0100 (CET) Received: from thoth.se.axis.com (unknown [10.0.2.173]) by boulder03.se.axis.com (Postfix) with ESMTP; Mon, 20 Nov 2017 14:32:40 +0100 (CET) Received: from lnxartpec1.se.axis.com (lnxartpec1.se.axis.com [10.88.4.10]) by thoth.se.axis.com (Postfix) with ESMTP id 2C8BE192E; Mon, 20 Nov 2017 14:32:40 +0100 (CET) Received: by lnxartpec1.se.axis.com (Postfix, from userid 20283) id 24ECE400FE; Mon, 20 Nov 2017 14:32:40 +0100 (CET) From: Niklas Cassel To: linux-arm-kernel@axis.com, linux-pci@vger.kernel.org, linux-omap@vger.kernel.org Cc: Niklas Cassel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v5 00/18] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Date: Mon, 20 Nov 2017 14:32:03 +0100 Message-Id: <20171120133222.27771-1-niklas.cassel@axis.com> X-Mailer: git-send-email 2.14.2 X-TM-AS-GCONF: 00 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This is a series that adds: - PCI endpoint mode support in the ARTPEC-6 driver. - ARTPEC-7 SoC support in the ARTPEC-6 driver (the SoCs are very similar). - Small fixes for MSI in designware-ep and designware-host, needed to get endpoint mode support working for ARTPEC-6. - Cleanups in pci-dra7xx to better prepare for endpoint mode in other DWC based PCIe drivers. New in V5: -Replaced ep->page_size with epc->mem->page_size in patch ("PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init") and in patch ("PCI: designware-ep: Add generic function for raising MSI irq"). -Included a new patch in this patch series: ("PCI: dwc: artpec6: Deassert the core before waiting for PHY"). Niklas Cassel (18): PCI: dwc: Use the DMA-API to get the MSI address PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar() PCI: designware-ep: Add generic function for raising MSI irq PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe PCI: dwc: dra7xx: Help compiler to remove unused code PCI: dwc: artpec6: Remove unused defines PCI: dwc: artpec6: Use BIT and GENMASK macros PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functions bindings: PCI: artpec: Add support for endpoint mode PCI: dwc: artpec6: Add support for endpoint mode PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument PCI: dwc: artpec6: Deassert the core before waiting for PHY bindings: PCI: artpec: Add support for the ARTPEC-7 SoC PCI: dwc: artpec6: Add support for the ARTPEC-7 SoC .../devicetree/bindings/pci/axis,artpec6-pcie.txt | 5 +- drivers/pci/dwc/Kconfig | 68 +-- drivers/pci/dwc/Makefile | 4 +- drivers/pci/dwc/pci-dra7xx.c | 27 +- drivers/pci/dwc/pcie-artpec6.c | 470 ++++++++++++++++++--- drivers/pci/dwc/pcie-designware-ep.c | 59 ++- drivers/pci/dwc/pcie-designware-host.c | 15 +- drivers/pci/dwc/pcie-designware.c | 2 +- drivers/pci/dwc/pcie-designware.h | 22 +- 9 files changed, 554 insertions(+), 118 deletions(-) -- 2.14.2 From 1584506700559843069@xxx Sun Nov 19 14:55:44 +0000 2017 X-GM-THRID: 1584506700559843069 X-Gmail-Labels: Inbox,Category Promotions,HistoricalUnread