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[209.132.180.67]) by mx.google.com with ESMTP id m26si8980928pli.826.2017.11.20.13.29.45; Mon, 20 Nov 2017 13:29:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753055AbdKTV2E (ORCPT + 67 others); Mon, 20 Nov 2017 16:28:04 -0500 Received: from mail-pg0-f66.google.com ([74.125.83.66]:36161 "EHLO mail-pg0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752720AbdKTV2C (ORCPT ); Mon, 20 Nov 2017 16:28:02 -0500 Received: by mail-pg0-f66.google.com with SMTP id k190so3738942pga.3 for ; Mon, 20 Nov 2017 13:28:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=7wy5YD5g/4hiu6kFmBUrLjXi0mgl9v1eT20yWrbP6cU=; b=X3FGD2yi8pLEgoQ37ghxxbY7gyA8qEDAKkwEfNKHgRmIHT9SpCAg3iWcuJSH3e1S3/ 8L5DKnvhR+nusCX3Fwjg+4pMADL9rc9od3hSt9Dn9j8tlDqBOKTintDoMwzPRDX/4rwP yGD1WkAeysAhAKWfagXDyMVZ6g8EdHJ+RD26ELYXCVNtEs+9Z4Assy5JFV+RE5y0yPaX cLOPSRQFbyqRlbU61dC+x1TkFKD3B62oMaWTGg6ueSmbnWR3d0KfSpeFSU6296oclRKe EeoWC+47cjkvM6FzQIN/PNDgMhySBS0/qMkejiUpLvxFEmXp1BGjVKwdkoCuknWpoqg1 zazg== X-Gm-Message-State: AJaThX5RrOV+VFWIJmFBDzmDQ/fhcfJZLW706txkXS/ogs4BO9P+3byD co3PMzjJGtTmwBTrtaFjzS4nsSyaY+w= X-Received: by 10.99.170.1 with SMTP id e1mr6644520pgf.242.1511213281811; Mon, 20 Nov 2017 13:28:01 -0800 (PST) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id v190sm17824046pgv.25.2017.11.20.13.28.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 20 Nov 2017 13:28:01 -0800 (PST) Date: Mon, 20 Nov 2017 13:28:01 -0800 (PST) X-Google-Original-Date: Mon, 20 Nov 2017 13:25:26 PST (-0800) Subject: Re: [patches] Re: [PATCH] dt-bindings: Add a RISC-V SBI firmware node In-Reply-To: <20171120202856.nptoirhm5luiamt7@latitude> CC: mark.rutland@arm.com, robh+dt@kernel.org, devicetree@vger.kernel.org, patches@groups.riscv.org, linux-kernel@vger.kernel.org, j.neuschaefer@gmx.net From: Palmer Dabbelt To: j.neuschaefer@gmx.net Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 20 Nov 2017 12:28:56 PST (-0800), j.neuschaefer@gmx.net wrote: > On Mon, Nov 20, 2017 at 11:50:00AM -0800, Palmer Dabbelt wrote: >> The RISC-V privileged ISA mandates the presence of an SBI, but there's >> no reason not to put it in the device tree. This would allow us to >> possibly remove the SBI later. > > Thanks! > >> >> CC: Jonathan Neuschäfer >> Signed-off-by: Palmer Dabbelt >> --- >> .../devicetree/bindings/firmware/riscv.sbi.txt | 20 ++++++++++++++++++++ >> 1 file changed, 20 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/firmware/riscv.sbi.txt >> >> diff --git a/Documentation/devicetree/bindings/firmware/riscv.sbi.txt b/Documentation/devicetree/bindings/firmware/riscv.sbi.txt >> new file mode 100644 >> index 000000000000..42384d5d52cf >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/firmware/riscv.sbi.txt > > Nit: Other bindings use either a comma (as in the compatible string, > "riscv,sbi.txt") or a dash (vendor-product.txt, "riscv-sbi.txt") in the > file name. That was just a typo, I'll fix it. >> @@ -0,0 +1,20 @@ >> +RISC-V Supervisor Binary Interface (SBI) >> + >> +The RISC-V privileged ISA specification mandates the presence of a supervisor >> +binary interface that performs some operations which might otherwise require >> +particularly complicated instructions. This interface includes >> +inter-processor interrupts, TLB flushes, i-cache and TLB shootdowns, a >> +console, and power management. >> + >> +Required properties: >> +- compatible: must contain one of the following >> + * "riscv,sbi" for the SBI defined by the privileged specification of the >> + system. > > "of the system" seems to imply that different RISC-V systems (different > RISC-V implementations) can have different privileged specifications. Actually, that was intentional -- I wrote it this way because different RISC-V systems do have different privileged specifications. The RISC-V specifications aren't frozen in time, they're just guaranteed to be compatible in the future. For example, the user ISA document has been updated multiple times (the C spec, eliminating some unspecified behavior) and will continue to be updated (V and other extensions, the memory model). The privileged spec will be updated in a compatible way just like the user spec will be -- I know there's at least hypervisor support in the works, and I saw some things to remove undefined behavior go past as well. In a similar fashion, the ABI and SBI will continue to evolve. For example, we'll probably add new system calls to extend the user ABI and new hyper calls to extend the SBI. > I think it's better to refer to concrete documents, that don't depend on > the rest of the system, instead. Either: > > * "riscv,sbi" for the SBI defined by the RISC-V Privileged ISA Specification. > > Or something like: > > * "sifive,sbi" for the SBI defined by SiFive document XYZ. > > > [ I know that there currently is no SBI spec, because the chapter has > been removed from the Priv Spec, but this can be fixed later, once > the final name of the document describing the SBI is clear. ] Ya, well, that's just a bug :). There'll eventually be a spec, but I don't think it changes the wording here. > >> + >> +Example: >> + >> +firmware { >> + sbi { >> + compatible = "riscv,sbi"; >> + }; >> +}; >> -- > > > Thanks, > Jonathan Neuschäfer > > -- > You received this message because you are subscribed to the Google Groups "RISC-V Patches" group. > To unsubscribe from this group and stop receiving emails from it, send an email to patches+unsubscribe@groups.riscv.org. > To post to this group, send email to patches@groups.riscv.org. > Visit this group at https://groups.google.com/a/groups.riscv.org/group/patches/. > To view this discussion on the web visit https://groups.google.com/a/groups.riscv.org/d/msgid/patches/20171120202856.nptoirhm5luiamt7%40latitude. > For more options, visit https://groups.google.com/a/groups.riscv.org/d/optout. From 1584618321848329270@xxx Mon Nov 20 20:29:54 +0000 2017 X-GM-THRID: 1584615981624343565 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread