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Subject: [PATCH] dt-bindings: Add a RISC-V SBI firmware node
Date:   Mon, 20 Nov 2017 11:50:00 -0800
Message-Id: <20171120195000.2070-1-palmer@sifive.com>
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Cc:     patches@groups.riscv.org, linux-kernel@vger.kernel.org,
        Palmer Dabbelt <palmer@sifive.com>,
        nathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
From:   Palmer Dabbelt <palmer@sifive.com>
To:     mark.rutland@arm.com, robh+dt@kernel.org,
        devicetree@vger.kernel.org
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

The RISC-V privileged ISA mandates the presence of an SBI, but there's
no reason not to put it in the device tree.  This would allow us to
possibly remove the SBI later.

CC: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 .../devicetree/bindings/firmware/riscv.sbi.txt       | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/firmware/riscv.sbi.txt

diff --git a/Documentation/devicetree/bindings/firmware/riscv.sbi.txt b/Documentation/devicetree/bindings/firmware/riscv.sbi.txt
new file mode 100644
index 000000000000..42384d5d52cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/riscv.sbi.txt
@@ -0,0 +1,20 @@
+RISC-V Supervisor Binary Interface (SBI)
+
+The RISC-V privileged ISA specification mandates the presence of a supervisor
+binary interface that performs some operations which might otherwise require
+particularly complicated instructions.  This interface includes
+inter-processor interrupts, TLB flushes, i-cache and TLB shootdowns, a
+console, and power management.
+
+Required properties:
+- compatible: must contain one of the following
+ * "riscv,sbi" for the SBI defined by the privileged specification of the
+   system.
+
+Example:
+
+firmware {
+	sbi {
+		compatible = "riscv,sbi";
+	};
+};
-- 
2.13.6


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