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[209.132.180.67]) by mx.google.com with ESMTP id l190si790031pgd.777.2017.11.16.04.37.26; Thu, 16 Nov 2017 04:37:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934704AbdKPMgA (ORCPT + 91 others); Thu, 16 Nov 2017 07:36:00 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:10932 "EHLO szxga04-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934658AbdKPMfm (ORCPT ); Thu, 16 Nov 2017 07:35:42 -0500 Received: from 172.30.72.58 (EHLO DGGEMS409-HUB.china.huawei.com) ([172.30.72.58]) by dggrg04-dlp.huawei.com (MOS 4.4.6-GA FastPath queued) with ESMTP id DKY66330; Thu, 16 Nov 2017 20:35:38 +0800 (CST) Received: from huawei.com (10.175.102.38) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.361.1; Thu, 16 Nov 2017 20:34:35 +0800 From: Tan Xiaojun To: , CC: Subject: [PATCH] drivers: base: cacheinfo: support DT overrides for cache type Date: Thu, 16 Nov 2017 20:58:09 +0800 Message-ID: <1510837089-5951-1-git-send-email-tanxiaojun@huawei.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.175.102.38] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.5A0D861B.005B,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 814ecee8ccac64f1413feec7a928433f Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Since commit dfea747d2aba ("drivers: base: cacheinfo: support DT overrides for cache properties"), we can set the correct cacheinfo via DT. But the cache type can't be set in the same way. I found this may be a problem in recent tests. I tested L3 cache node setting in DT in Hisilicon D03/D05 board. And I got cacheinfo via sysfs below: $ cat /sys/devices/system/cpu/cpu*/cache/index3/ allocation_policy level power/ shared_cpu_map uevent write_policy coherency_line_size number_of_sets shared_cpu_list size ways_of_associativity This is incomplete, no type file to display type info. Because L3 cache is uncore, we can't get correct type info from system register, and will get a default type "CACHE_TYPE_NOCACHE". Then use "lscpu" will print an error like below: $ lscpu lscpu: cannot open /sys/devices/system/cpu/cpu0/cache/index3/type: No such file or directory So I think maybe we can set correct cache type via DT too. Signed-off-by: Tan Xiaojun --- drivers/base/cacheinfo.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index eb3af27..3e650dc 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -122,6 +122,15 @@ static inline int get_cacheinfo_idx(enum cache_type type) return type; } +static void cache_type(struct cacheinfo *this_leaf) +{ + const __be32 *cache_type; + + cache_type = of_get_property(this_leaf->of_node, "type", NULL); + if (cache_type) + this_leaf->type = of_read_number(cache_type, 1); +} + static void cache_size(struct cacheinfo *this_leaf) { const char *propname; @@ -194,6 +203,7 @@ static void cache_of_override_properties(unsigned int cpu) for (index = 0; index < cache_leaves(cpu); index++) { this_leaf = this_cpu_ci->info_list + index; + cache_type(this_leaf); cache_size(this_leaf); cache_get_line_size(this_leaf); cache_nr_sets(this_leaf); -- 2.7.4 From 1584598785145749180@xxx Mon Nov 20 15:19:23 +0000 2017 X-GM-THRID: 1584598785145749180 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread