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From:   Xie XiuQi <xiexiuqi@huawei.com>
To:     <tony.luck@intel.com>, <bp@alien8.de>
CC:     <tglx@linutronix.de>, <mingo@redhat.com>, <hpa@zytor.com>,
        <x86@kernel.org>, <linux-edac@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <xiexiuqi@huawei.com>
Subject: [PATCH] x86/mce: add support SRAO reported via CMC check
Date:   Tue, 14 Nov 2017 13:55:11 +0800
Message-ID: <1510638911-88703-1-git-send-email-xiexiuqi@huawei.com>
MIME-Version: 1.0
Content-Type: text/plain
Sender: linux-kernel-owner@vger.kernel.org
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In Intel SDM Volume 3B (253669-063US, July 2017), SRAO could be
reported via CMC:

  In cases when SRAO is signaled via CMCI the error signature is
  indicated via UC=1, PCC=0, S=0.

So we add those known AO MCACODs check in mce_severity().

Signed-off-by: Xie XiuQi <xiexiuqi@huawei.com>
Tested-by: Chen Wei <chenwei68@huawei.com>
---
 arch/x86/kernel/cpu/mcheck/mce-severity.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 4ca632a..48f239a 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -101,6 +101,16 @@
 		NOSER, BITCLR(MCI_STATUS_UC)
 		),
 
+	/* known AO MCACODs reported via CMC: */
+	MCESEV(
+		AO, "Action optional: memory scrubbing error",
+		SER, MASK(MCI_UC_SAR|MCACOD_SCRUBMSK, MCI_STATUS_UC|MCACOD_SCRUB)
+		),
+	MCESEV(
+		AO, "Action optional: last level cache writeback error",
+		SER, MASK(MCI_UC_SAR|MCACOD, MCI_STATUS_UC|MCACOD_L3WB)
+		),
+
 	/* ignore OVER for UCNA */
 	MCESEV(
 		UCNA, "Uncorrected no action required",
-- 
1.8.3.1


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