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[209.132.180.67]) by mx.google.com with ESMTP id d17si16373772pge.191.2017.11.14.16.37.03; Tue, 14 Nov 2017 16:37:16 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=WixcWMdv; dkim=pass header.i=@codeaurora.org header.s=default header.b=Uff7dLcI; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756484AbdKOAf3 (ORCPT + 87 others); Tue, 14 Nov 2017 19:35:29 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:39228 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754772AbdKOAfX (ORCPT ); Tue, 14 Nov 2017 19:35:23 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 36D776081B; Wed, 15 Nov 2017 00:35:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1510706123; bh=k2roMeUvX6o4ffjNjVW6Vc6QFON76tSo58jSmlnaW8s=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=WixcWMdvP9+jmdtThpVEArcALX8aIO8szbNvSXi1WEfn4YteVWF6cC3RDdFqPTtK+ PySx0k3mrGmhk02b6jaNzADDw6OLKcU+CDweB3HLCWGxAnWpOhpteMQSPsisL9OtJB SJ178JMvAksQ5WmVW2u2n/qHn6x28atbG18Ccuh0= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from localhost (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id AD58460718; Wed, 15 Nov 2017 00:35:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1510706122; bh=k2roMeUvX6o4ffjNjVW6Vc6QFON76tSo58jSmlnaW8s=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Uff7dLcIg4dh5auh9OzBGQ4iVTTMHZthgV2SHkOlyiReOpXCrdXzRU9v9ldO7q4tI Rzr1OHHjgQvppWGbQeYKL9/CshMQE9ywss/tdH5ZsoySrcN2hrZqDMwdTOEyQCyPlz uBjoAFOKahLOQ35spoJRfBngLqFAfGRe/nRI6oDs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org AD58460718 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=sboyd@codeaurora.org Date: Tue, 14 Nov 2017 16:35:22 -0800 From: Stephen Boyd To: Catalin Marinas Cc: Will Deacon , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH] arm64: cpu_errata: Add Kryo to Falkor 1003 errata Message-ID: <20171115003522.GL11955@codeaurora.org> References: <20171108190029.19835-1-sboyd@codeaurora.org> <20171110172656.zvnpfjkky7rqumyf@armageddon.cambridge.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171110172656.zvnpfjkky7rqumyf@armageddon.cambridge.arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/10, Catalin Marinas wrote: > On Wed, Nov 08, 2017 at 11:00:29AM -0800, Stephen Boyd wrote: > > The Kryo CPUs are also affected by the Falkor 1003 errata, so > > we need to do the same workaround on Kryo CPUs. The MIDR is > > slightly more complicated here, where the PART number is not > > always the same when looking at all the bits from 15 to 4. Drop > > the lower 8 bits and just look at the top 4 to see if it's '2' > > and then consider those as Kryo CPUs. This covers all the > > combinations without having to list them all out. > > > > Signed-off-by: Stephen Boyd > > --- > > > > We may need to introduce another Kconfig option to block software PAN > > from being enabled when this errata is enabled (and then have software PAN > > depend on this new config being false). > > It depends on whether you'd want to use SW PAN together with these CPUs. > From a defconfig + single Image perspective, SW PAN is disabled but it > would be nice to allow single Image with both E1003 and SW PAN configs > enabled (though SW PAN wouldn't be used at run-time). > > As a quick hack, something like below but we may want to add a separate > cap bit as a minor optimisation (not sure it makes a difference). > Untested: Ok. The Falkor CPUs support HW PAN so your patch looks like it should work. If we're running on a Kryo CPU we may not see the HW PAN capability and then we would still return false here because the errata is present. I'll fold it in and test it out. > > ------------------8<-------------------------- > diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h > index ac67cfc2585a..8d2ddaef70a2 100644 > --- a/arch/arm64/include/asm/cpufeature.h > +++ b/arch/arm64/include/asm/cpufeature.h > @@ -268,7 +268,8 @@ static inline bool system_supports_fpsimd(void) > static inline bool system_uses_ttbr0_pan(void) > { > return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) && > - !cpus_have_const_cap(ARM64_HAS_PAN); > + !cpus_have_const_cap(ARM64_HAS_PAN) && > + !cpus_have_const_cap(ARM64_WORKAROUND_QCOM_FALKOR_E1003); > } > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From 1583700896889993075@xxx Fri Nov 10 17:27:50 +0000 2017 X-GM-THRID: 1583525619010859747 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread