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Subject: Re: [PATCH 2/4] drm: amd: Fix line continuation formats
To:     Joe Perches <joe@perches.com>, linux-kernel@vger.kernel.org
Cc:     Alex Deucher <alexander.deucher@amd.com>,
        David Airlie <airlied@linux.ie>,
        dri-devel@lists.freedesktop.org,
        =?UTF-8?Q?Christian_K=c3=b6nig?= <christian.koenig@amd.com>,
        amd-gfx@lists.freedesktop.org
References: <cover.1510845910.git.joe@perches.com>
 <eee8836696843f983a9533d6441fa9f2d8cbe92f.1510845910.git.joe@perches.com>
From:   Harry Wentland <harry.wentland@amd.com>
Message-ID: <1b2c63b7-319a-caab-6809-197784c179ef@amd.com>
Date:   Thu, 16 Nov 2017 10:38:41 -0500
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On 2017-11-16 10:27 AM, Joe Perches wrote:
> Line continuations with excess spacing causes unexpected output.
> 
> Miscellanea:
> 
> o Added missing '\n' to a few of the coalesced pr_<level> formats
> 
> Signed-off-by: Joe Perches <joe@perches.com>
> ---
>  drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c   | 11 ++++-----
>  .../amd/powerplay/hwmgr/process_pptables_v1_0.c    |  6 ++---
>  drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 27 ++++++++--------------
>  drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c   |  6 ++---
>  .../gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c  |  9 +++-----
>  .../gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c   |  6 ++---
>  6 files changed, 22 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> index ced42484dcfc..6743786afcce 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
> @@ -220,8 +220,7 @@ static void dpcd_set_lt_pattern_and_lane_settings(
>  		size_in_bytes);
>  
>  	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
> -		"%s:\n %x VS set = %x  PE set = %x \
> -		max VS Reached = %x  max PE Reached = %x\n",
> +		"%s:\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
>  		__func__,
>  		DP_TRAINING_LANE0_SET,
>  		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
> @@ -558,8 +557,7 @@ static void dpcd_set_lane_settings(
>  	*/
>  
>  	dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING,
> -		"%s\n %x VS set = %x  PE set = %x \
> -		max VS Reached = %x  max PE Reached = %x\n",
> +		"%s\n %x VS set = %x  PE set = %x max VS Reached = %x  max PE Reached = %x\n",
>  		__func__,
>  		DP_TRAINING_LANE0_SET,
>  		dpcd_lane[0].bits.VOLTAGE_SWING_SET,
> @@ -872,9 +870,8 @@ static bool perform_clock_recovery_sequence(
>  	if (retry_count >= LINK_TRAINING_MAX_CR_RETRY) {
>  		ASSERT(0);
>  		dm_logger_write(link->ctx->logger, LOG_ERROR,
> -			"%s: Link Training Error, could not \
> -			 get CR after %d tries. \
> -			Possibly voltage swing issue", __func__,
> +			"%s: Link Training Error, could not get CR after %d tries. Possibly voltage swing issue",

Would probably be good to add a '\n' here as well but that's not the main intention of this patch.

Either way patch is
Reviewed-by: Harry Wentland <harry.wentland@amd.com>

Harry

> +			__func__,
>  			LINK_TRAINING_MAX_CR_RETRY);
>  
>  	}
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> index d1af1483c69b..813f827e4270 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c
> @@ -523,8 +523,7 @@ static int get_pcie_table(
>  		if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
>  			pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
>  		else
> -			pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
> -			Disregarding the excess entries... \n");
> +			pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n");
>  
>  		pcie_table->count = pcie_count;
>  		for (i = 0; i < pcie_count; i++) {
> @@ -563,8 +562,7 @@ static int get_pcie_table(
>  		if ((uint32_t)atom_pcie_table->ucNumEntries <= pcie_count)
>  			pcie_count = (uint32_t)atom_pcie_table->ucNumEntries;
>  		else
> -			pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! \
> -			Disregarding the excess entries... \n");
> +			pr_err("Number of Pcie Entries exceed the number of SCLK Dpm Levels! Disregarding the excess entries...\n");
>  
>  		pcie_table->count = pcie_count;
>  
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> index 4f79c21f27ed..9599fe0ba779 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
> @@ -546,8 +546,7 @@ static void vega10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr,
>  	}
>  
>  	if (*voltage > ATOM_VIRTUAL_VOLTAGE_ID0)
> -		pr_info("Voltage value looks like a Leakage ID \
> -				but it's not patched\n");
> +		pr_info("Voltage value looks like a Leakage ID but it's not patched\n");
>  }
>  
>  /**
> @@ -701,18 +700,14 @@ static int vega10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
>  			table_info->vdd_dep_on_mclk;
>  
>  	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table,
> -		"VDD dependency on SCLK table is missing. \
> -		This table is mandatory", return -EINVAL);
> +		"VDD dependency on SCLK table is missing. This table is mandatory", return -EINVAL);
>  	PP_ASSERT_WITH_CODE(allowed_sclk_vdd_table->count >= 1,
> -		"VDD dependency on SCLK table is empty. \
> -		This table is mandatory", return -EINVAL);
> +		"VDD dependency on SCLK table is empty. This table is mandatory", return -EINVAL);
>  
>  	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table,
> -		"VDD dependency on MCLK table is missing. \
> -		This table is mandatory", return -EINVAL);
> +		"VDD dependency on MCLK table is missing.  This table is mandatory", return -EINVAL);
>  	PP_ASSERT_WITH_CODE(allowed_mclk_vdd_table->count >= 1,
> -		"VDD dependency on MCLK table is empty. \
> -		This table is mandatory", return -EINVAL);
> +		"VDD dependency on MCLK table is empty.  This table is mandatory", return -EINVAL);
>  
>  	table_info->max_clock_voltage_on_ac.sclk =
>  		allowed_sclk_vdd_table->entries[allowed_sclk_vdd_table->count - 1].clk;
> @@ -3415,8 +3410,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
>  					DPMTABLE_OD_UPDATE_SCLK)) {
>  			result = vega10_populate_all_graphic_levels(hwmgr);
>  			PP_ASSERT_WITH_CODE(!result,
> -					"Failed to populate SCLK during \
> -					PopulateNewDPMClocksStates Function!",
> +					"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
>  					return result);
>  		}
>  
> @@ -3425,8 +3419,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
>  					DPMTABLE_OD_UPDATE_MCLK)){
>  			result = vega10_populate_all_memory_levels(hwmgr);
>  			PP_ASSERT_WITH_CODE(!result,
> -					"Failed to populate MCLK during \
> -					PopulateNewDPMClocksStates Function!",
> +					"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
>  					return result);
>  		}
>  	} else {
> @@ -3543,8 +3536,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
>  			data->apply_optimized_settings) {
>  			result = vega10_populate_all_graphic_levels(hwmgr);
>  			PP_ASSERT_WITH_CODE(!result,
> -					"Failed to populate SCLK during \
> -					PopulateNewDPMClocksStates Function!",
> +					"Failed to populate SCLK during PopulateNewDPMClocksStates Function!",
>  					return result);
>  		}
>  
> @@ -3552,8 +3544,7 @@ static int vega10_populate_and_upload_sclk_mclk_dpm_levels(
>  				(DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) {
>  			result = vega10_populate_all_memory_levels(hwmgr);
>  			PP_ASSERT_WITH_CODE(!result,
> -					"Failed to populate MCLK during \
> -					PopulateNewDPMClocksStates Function!",
> +					"Failed to populate MCLK during PopulateNewDPMClocksStates Function!",
>  					return result);
>  		}
>  	}
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> index 4d672cd15785..ed4b37e566a3 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c
> @@ -1732,8 +1732,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
>  
>  	if (0 != result) {
>  		smu_data->smc_state_table.GraphicsBootLevel = 0;
> -		pr_err("VBIOS did not find boot engine clock value \
> -			in dependency table. Using Graphics DPM level 0!");
> +		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
>  		result = 0;
>  	}
>  
> @@ -1743,8 +1742,7 @@ static int ci_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
>  
>  	if (0 != result) {
>  		smu_data->smc_state_table.MemoryBootLevel = 0;
> -		pr_err("VBIOS did not find boot engine clock value \
> -			in dependency table. Using Memory DPM level 0!");
> +		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
>  		result = 0;
>  	}
>  
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> index 34128822b8fb..2ff682d44e8c 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c
> @@ -911,8 +911,7 @@ static int iceland_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
>  		hwmgr->dyn_state.vddc_dependency_on_sclk, engine_clock,
>  		&graphic_level->MinVddc);
>  	PP_ASSERT_WITH_CODE((0 == result),
> -		"can not find VDDC voltage value for VDDC	\
> -		engine clock dependency table", return result);
> +		"can not find VDDC voltage value for VDDC engine clock dependency table", return result);
>  
>  	/* SCLK frequency in units of 10KHz*/
>  	graphic_level->SclkFrequency = engine_clock;
> @@ -1678,8 +1677,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
>  
>  	if (0 != result) {
>  		smu_data->smc_state_table.GraphicsBootLevel = 0;
> -		pr_err("VBIOS did not find boot engine clock value \
> -			in dependency table. Using Graphics DPM level 0!");
> +		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Graphics DPM level 0!\n");
>  		result = 0;
>  	}
>  
> @@ -1689,8 +1687,7 @@ static int iceland_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
>  
>  	if (0 != result) {
>  		smu_data->smc_state_table.MemoryBootLevel = 0;
> -		pr_err("VBIOS did not find boot engine clock value \
> -			in dependency table. Using Memory DPM level 0!");
> +		pr_err("VBIOS did not find boot engine clock value in dependency table. Using Memory DPM level 0!\n");
>  		result = 0;
>  	}
>  
> diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> index 2f979fb86824..f6f39d01d227 100644
> --- a/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/smumgr/vega10_smumgr.c
> @@ -381,10 +381,8 @@ static int vega10_verify_smc_interface(struct pp_hwmgr *hwmgr)
>  		(rev_id == 0xc1) ||
>  		(rev_id == 0xc3)))) {
>  		if (smc_driver_if_version != SMU9_DRIVER_IF_VERSION) {
> -			pr_err("Your firmware(0x%x) doesn't match \
> -				SMU9_DRIVER_IF_VERSION(0x%x). \
> -				Please update your firmware!\n",
> -				smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
> +			pr_err("Your firmware(0x%x) doesn't match SMU9_DRIVER_IF_VERSION(0x%x). Please update your firmware!\n",
> +			       smc_driver_if_version, SMU9_DRIVER_IF_VERSION);
>  			return -EINVAL;
>  		}
>  	}
> 

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