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[209.132.180.67]) by mx.google.com with ESMTP id d10si420940pgo.497.2017.11.15.23.49.29; Wed, 15 Nov 2017 23:49:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933451AbdKPHs0 (ORCPT + 91 others); Thu, 16 Nov 2017 02:48:26 -0500 Received: from david.siemens.de ([192.35.17.14]:50092 "EHLO david.siemens.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759392AbdKPHrk (ORCPT ); Thu, 16 Nov 2017 02:47:40 -0500 Received: from mail1.siemens.de (mail1.siemens.de [139.23.33.14]) by david.siemens.de (8.15.2/8.15.2) with ESMTPS id vAG7Qurr009690 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 Nov 2017 08:26:57 +0100 Received: from md1f2u6c.ww002.siemens.net ([167.87.32.158]) by mail1.siemens.de (8.15.2/8.15.2) with ESMTP id vAG7QrlY029336; Thu, 16 Nov 2017 08:26:56 +0100 From: Jan Kiszka To: Thomas Gleixner , Ingo Molnar , "H . Peter Anvin" Cc: x86@kernel.org, Linux Kernel Mailing List , jailhouse-dev@googlegroups.com Subject: [PATCH 09/10] x86: jailhouse: Wire up IOAPIC for legacy UART ports Date: Thu, 16 Nov 2017 08:26:51 +0100 Message-Id: X-Mailer: git-send-email 2.12.3 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Jan Kiszka The typical I/O interrupts in non-root cells are MSI-based. However, the platform UARTs do not support MSI. In order to run a non-root cell that shall be use one of them, we need to register the standard IOAPIC and set 1:1 routing for IRQ 3 and 4. If an IOAPIC is not available, the boot loader clears standard_ioapic in the setup data, and we skip the registration. If we should not be allowed to use one of those pins, Jailhouse will simply ignore our accesses. Signed-off-by: Jan Kiszka --- arch/x86/kernel/jailhouse.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c index 0bcca175c35e..05459ea0ecc7 100644 --- a/arch/x86/kernel/jailhouse.c +++ b/arch/x86/kernel/jailhouse.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include @@ -148,6 +149,14 @@ static unsigned int x2apic_get_apic_id(unsigned long id) static void __init jailhouse_init_platform(void) { + struct ioapic_domain_cfg ioapic_cfg = { + .type = IOAPIC_DOMAIN_STRICT, + .ops = &mp_ioapic_irqdomain_ops, + }; + struct mpc_intsrc mp_irq = { + .type = MP_INTSRC, + .irqtype = mp_INT, + }; u64 pa_data = boot_params.hdr.setup_data; struct jailhouse_setup_data *data; unsigned int cpu; @@ -189,6 +198,17 @@ static void __init jailhouse_init_platform(void) boot_cpu_apic_version); smp_found_config = 1; + if (data->standard_ioapic) { + mp_register_ioapic(0, 0xfec00000, gsi_top, &ioapic_cfg); + + /* Register 1:1 mapping for legacy UART IRQs 3 and 4 */ + mp_irq.srcbusirq = mp_irq.dstirq = 3; + mp_save_irq(&mp_irq); + + mp_irq.srcbusirq = mp_irq.dstirq = 4; + mp_save_irq(&mp_irq); + } + early_memunmap(data, sizeof(*data)); /* -- 2.12.3 From 1584280105999469318@xxx Fri Nov 17 02:54:07 +0000 2017 X-GM-THRID: 1584280105999469318 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread