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[209.132.180.67]) by mx.google.com with ESMTP id bg5si106217plb.458.2017.11.13.05.03.22; Mon, 13 Nov 2017 05:03:35 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754644AbdKMNBY (ORCPT + 95 others); Mon, 13 Nov 2017 08:01:24 -0500 Received: from mail.linuxfoundation.org ([140.211.169.12]:50172 "EHLO mail.linuxfoundation.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753633AbdKMNBS (ORCPT ); Mon, 13 Nov 2017 08:01:18 -0500 Received: from localhost (LFbn-1-12253-150.w90-92.abo.wanadoo.fr [90.92.67.150]) by mail.linuxfoundation.org (Postfix) with ESMTPSA id A89F0AA6; Mon, 13 Nov 2017 13:01:17 +0000 (UTC) From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Thomas Petazzoni , Stephen Boyd , Sasha Levin Subject: [PATCH 4.9 47/87] clk: mvebu: adjust AP806 CPU clock frequencies to production chip Date: Mon, 13 Nov 2017 13:56:04 +0100 Message-Id: <20171113125619.711566511@linuxfoundation.org> X-Mailer: git-send-email 2.15.0 In-Reply-To: <20171113125615.304035578@linuxfoundation.org> References: <20171113125615.304035578@linuxfoundation.org> User-Agent: quilt/0.65 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 4.9-stable review patch. If anyone has any objections, please let me know. ------------------ From: Thomas Petazzoni [ Upstream commit 0c70ffc5f300e7c3a1a76ca0530860574afc890b ] This commit adjusts the list of possible "Sample At Reset" values that define the CPU clock frequency of the AP806 (part of Marvell Armada 7K/8K) to the values that have been validated with the production chip. Earlier values were preliminary. Signed-off-by: Thomas Petazzoni Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin Signed-off-by: Greg Kroah-Hartman --- drivers/clk/mvebu/ap806-system-controller.c | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) --- a/drivers/clk/mvebu/ap806-system-controller.c +++ b/drivers/clk/mvebu/ap806-system-controller.c @@ -55,21 +55,39 @@ static int ap806_syscon_clk_probe(struct freq_mode = reg & AP806_SAR_CLKFREQ_MODE_MASK; switch (freq_mode) { - case 0x0 ... 0x5: + case 0x0: + case 0x1: cpuclk_freq = 2000; break; - case 0x6 ... 0xB: + case 0x6: + case 0x7: cpuclk_freq = 1800; break; - case 0xC ... 0x11: + case 0x4: + case 0xB: + case 0xD: cpuclk_freq = 1600; break; - case 0x12 ... 0x16: + case 0x1a: cpuclk_freq = 1400; break; - case 0x17 ... 0x19: + case 0x14: + case 0x17: cpuclk_freq = 1300; break; + case 0x19: + cpuclk_freq = 1200; + break; + case 0x13: + case 0x1d: + cpuclk_freq = 1000; + break; + case 0x1c: + cpuclk_freq = 800; + break; + case 0x1b: + cpuclk_freq = 600; + break; default: dev_err(&pdev->dev, "invalid SAR value\n"); return -EINVAL; From 1583957850388571704@xxx Mon Nov 13 13:32:00 +0000 2017 X-GM-THRID: 1583957096921633729 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread