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[209.132.180.67]) by mx.google.com with ESMTP id d10si12723406pgc.100.2017.11.12.17.43.45; Sun, 12 Nov 2017 17:43:57 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=kHq6uShk; dkim=pass header.i=@codeaurora.org header.s=default header.b=iKbqqX0N; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751767AbdKMBms (ORCPT + 87 others); Sun, 12 Nov 2017 20:42:48 -0500 Received: from smtp.codeaurora.org ([198.145.29.96]:49120 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751638AbdKMBmp (ORCPT ); Sun, 12 Nov 2017 20:42:45 -0500 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 32DD16083D; Mon, 13 Nov 2017 01:42:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1510537365; bh=ZWBd6W/3LZ7J6JU8CEIFc34fihZIGLWLmm858am7XF8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kHq6uShk/ndZPApQ8vFLQh9mPoKonDyGBEHBqBCCFkMDGNSu1hIH1uPxwezEH84W8 bjoRIATAZ6flQn1K8rxuqw6USDlKF9+/6o6jQd47zr1d2cVMR6B3Hxbdd3z7oq6PEs lD/o2P6jb2MnvsOFwfBH/8TPFwfpBXUA7K2pNN8M= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from shankerd-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: shankerd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B38FB6024A; Mon, 13 Nov 2017 01:42:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1510537363; bh=ZWBd6W/3LZ7J6JU8CEIFc34fihZIGLWLmm858am7XF8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iKbqqX0N0b+tAJ3qCWJRZHClKz1PC5IaRL8CsMFAww478g1WWeKVpX0oII5eC/a82 lNPhp2L/sJ8GFLU4gbOFL4F4p9XKLqw2HHVqUJZCfLA8mxF3zD4Jul7q+DtRjsYSjA xOQLGjn+vQeqRVH5YZ8Yr0JlPKLk1gYsIVpl5ono= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B38FB6024A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org From: Shanker Donthineni To: Will Deacon , Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , James Morse , Robin Murphy , Ard Biesheuvel , Matt Fleming , Christoffer Dall , linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Shanker Donthineni Subject: [PATCH v3 1/2] arm64: Define cputype macros for Falkor CPU Date: Sun, 12 Nov 2017 19:42:38 -0600 Message-Id: <1510537359-9978-2-git-send-email-shankerd@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1510537359-9978-1-git-send-email-shankerd@codeaurora.org> References: <1510537359-9978-1-git-send-email-shankerd@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add cputype definition macros for Qualcomm Datacenter Technologies Falkor CPU in cputype.h. It's unfortunate that the first revision of the Falkor CPU used the wrong part number 0x800, got fixed in v2 chip with part number 0xC00, and would be used the same value for future revisions. Signed-off-by: Shanker Donthineni --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d..cbf08d7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -91,6 +91,7 @@ #define BRCM_CPU_PART_VULCAN 0x516 #define QCOM_CPU_PART_FALKOR_V1 0x800 +#define QCOM_CPU_PART_FALKOR 0xC00 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) @@ -99,6 +100,7 @@ #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) +#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) #ifndef __ASSEMBLY__ -- Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From 1583911664578478010@xxx Mon Nov 13 01:17:53 +0000 2017 X-GM-THRID: 1583911664578478010 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread