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Date:   Thu, 09 Nov 2017 13:54:27 -0800 (PST)
Subject:     Re: [patches] [PATCH 0/2] riscv: pass endianness and machine size to sparse
In-Reply-To: <CAExDi1RVYb-uDR=8LC9oRTtP=Mzx=g_XdqkLV6KFqx7jQMT5fA@mail.gmail.com>
CC:     albert@sifive.com, patches@groups.riscv.org,
        linux-kernel@vger.kernel.org
From:   Palmer Dabbelt <palmer@sifive.com>
To:     luc.vanoostenryck@gmail.com
Message-ID: <mhng-88e8e706-1ac7-4a09-ab59-e212a101c6fa@palmer-si-x1c4>
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On Thu, 09 Nov 2017 13:46:50 PST (-0800), luc.vanoostenryck@gmail.com wrote:
> On Thu, Nov 9, 2017 at 10:36 PM, Palmer Dabbelt <palmer@sifive.com> wrote:
>> On Wed, 08 Nov 2017 21:53:52 PST (-0800), luc.vanoostenryck@gmail.com wrote:
>>> The goal of these two patches is to ass endianness and machine
>>> size info to sparse so that sparse can emit correct diagnostics
>>> even when the endianness and machine size doesn't correspond to
>>> sparse's defaults.
>>>
>>> Luc Van Oostenryck (2):
>>>   riscv: pass endianness info to sparse
>>>   riscv: pass machine size to sparse
>>>
>>>  arch/riscv/Makefile | 4 ++++
>>>  1 file changed, 4 insertions(+)
>>
>> Thanks!  I'll take these into the RISC-V tree.
>
> Well, better to hold one because someone has asked
> to treat the problem in a generic way (the same problem exist
> on other archs) and I certainly think it's indeed better.
>
> I'll sent a newer patch in a day or two.

OK, no problem.  I'm re-organizing our big list of outstanding patches (in
addition the reviewed ones I'll be sending up), so I'll just leave this on a
staging branch.

Thanks!

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