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From:   Wanpeng Li <kernellwp@gmail.com>
Date:   Thu, 9 Nov 2017 18:47:44 +0800
Message-ID: <CANRm+CyCk91aVTa9zG75Op9PCN71ZEkwt9-h16=WktEZ6reiTA@mail.gmail.com>
Subject: Re: [PATCH v5 3/3] KVM: nVMX: Fix mmu context after VMLAUNCH/VMRESUME failure
To:     Paolo Bonzini <pbonzini@redhat.com>
Cc:     Jim Mattson <jmattson@google.com>,
        Krish Sadhukhan <krish.sadhukhan@oracle.com>,
        LKML <linux-kernel@vger.kernel.org>,
        kvm list <kvm@vger.kernel.org>,
        =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= <rkrcmar@redhat.com>,
        Wanpeng Li <wanpeng.li@hotmail.com>
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2017-11-09 18:40 GMT+08:00 Paolo Bonzini <pbonzini@redhat.com>:
> On 09/11/2017 01:37, Wanpeng Li wrote:
>> 2017-11-09 5:47 GMT+08:00 Jim Mattson <jmattson@google.com>:
>>> I realize now that there are actually many other problems with
>>> deferring some control field checks to the hardware VM-entry of
>>> vmcs02. When there is an invalid control field, the vCPU should just
>>> fall through to the next instruction, without any state modifiation
>>> other than the ALU flags and the VM-instruction error field of the
>>> current VMCS. However, in preparation for the hardware VM-entry of
>>> vmcs02, we have already changed quite a bit of the vCPU state: the
>>> MSRs on the VM-entry MSR-load list, DR7, IA32_DEBUGCTL, the entire
>>> FLAGS register, etc. All of these changes should be undone, and we're
>>> not prepared to do that. (For instance, what was the old DR7 value
>>> that needs to be restored?)
>> I didn't observe real issue currently, and I hope this patchset can
>> catch the upcoming merge window. Then we can dig more into your
>> concern.
>
> Can any of you write a simple testcase for just one bug (e.g. DR7)?

Jim you can have a try for your concern, I have already tried tons of
stress testing and didn't observe any issue.

Regards,
Wanpeng Li

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