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[209.132.180.67]) by mx.google.com with ESMTP id n10si4908949plp.726.2017.11.09.01.44.34; Thu, 09 Nov 2017 01:44:45 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=C9kk/f1e; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753433AbdKIJny (ORCPT + 82 others); Thu, 9 Nov 2017 04:43:54 -0500 Received: from mail-ua0-f194.google.com ([209.85.217.194]:51961 "EHLO mail-ua0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752902AbdKIJnw (ORCPT ); Thu, 9 Nov 2017 04:43:52 -0500 Received: by mail-ua0-f194.google.com with SMTP id 65so3951801uaq.8; Thu, 09 Nov 2017 01:43:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=E+8CT5ilu7FSY+YelrPP7i11ZbWCR38UaLSZvGJPE78=; b=C9kk/f1eIweg1VVxPr9cGQv+1GXmL1fD8sirMLfiy97BLzStS+8Hcvg8fwBNbwicPl x/zpaSe/jwc26PsKQMiZRcGoK9Zo0MJk4ScF02slmcQdtDP+mmlO00JcgY6vkBoALoJs hnJ3m+0RmD1SupNofPWuDdIobvW5frerCC4lw2qDI5JdCc0EmqRrc7EZwP4h3tMWrtT0 5/wJU2EvnZUkvSzvMwSqEihoSSY7O5KmyWMrOBcARByuS3q6oC7J2oFUv2geRkrJgrWg W3FyBlvFAA0VY2NuN9R5/g0pTzCxvI3aFlzUVItVBF46xGa4cLayrR195U9aY43QJNQS TNXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=E+8CT5ilu7FSY+YelrPP7i11ZbWCR38UaLSZvGJPE78=; b=WgH3LbZbfCQJ6p9gtpLMX2rUAv/VlpdtUU0lnK8YroPKNfqRfaLsdazqRWVZnScp0w +vXWOHlEvauk6C2zN7adhWEnZm6A4Lra3UfsO4PmXBA55LgA8Gu0Bh/e2I1P5XmdFdJ0 wMbNPNWfq0ALFP0clWF6ZAXPQbyh0hmui/60XJWzcb5sIvrtRByCyfUws3Cl2SawR+qd MECAOJM8+GntEd5NYYGnebRLVD+kGx9EYvfg09PNzVOrYwfFHVTPyIhUXQpZ1Ka7X2/i m9y42Q29I86jg74cWvtRKMpcfUK1p/rKuGhtfiZN8t9xZ5iQIzuH2lmNUZ65ZbAntl+3 4byg== X-Gm-Message-State: AJaThX47QdiAUVgatr/ADj+JimBkU+PVhjpJk5TFj2L1pLsYUETjPcAJ BBA5NiHqIEpR+eCbhID5VHMIAbTedOAaZG2h5dQ= X-Received: by 10.176.83.206 with SMTP id l14mr2915165uaa.167.1510220631251; Thu, 09 Nov 2017 01:43:51 -0800 (PST) MIME-Version: 1.0 Received: by 10.159.62.8 with HTTP; Thu, 9 Nov 2017 01:43:10 -0800 (PST) In-Reply-To: References: From: Greentime Hu Date: Thu, 9 Nov 2017 17:43:10 +0800 Message-ID: Subject: Re: [PATCH 27/31] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller To: Rob Herring Cc: Greentime , "linux-kernel@vger.kernel.org" , Arnd Bergmann , "linux-arch@vger.kernel.org" , Thomas Gleixner , Jason Cooper , Marc Zyngier , netdev , Rick Chen , "devicetree@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 2017-11-08 21:25 GMT+08:00 Rob Herring : > +DT list > > On Tue, Nov 7, 2017 at 11:55 PM, Greentime Hu wrote: >> From: Greentime Hu > > Commit msg needed. Thanks. I will add commit msg in the next version patch. >> Signed-off-by: Rick Chen >> Signed-off-by: Greentime Hu >> --- >> .../interrupt-controller/andestech,ativic32.txt | 27 ++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt >> >> diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt >> new file mode 100644 >> index 0000000..6bac908 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt >> @@ -0,0 +1,27 @@ >> +* Andestech Internal Vector Interrupt Controller >> + >> +The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller >> +suitable for a simpler SoC platform not requiring a more sophisticated and >> +bigger External Vector Interrupt Controller. >> + >> + >> +Main node required properties: >> + >> +- compatible : should at least contain "andestech,ativic32". >> +- interrupt-parent: Empty for the interrupt controller itself > > Drop this. Thanks. I will fix it in the next version patch. >> +- interrupt-controller : Identifies the node as an interrupt controller >> +- #interrupt-cells: The number of cells to define the interrupts. Should be 2. >> + The first cell is the IRQ number >> + The second cell is used to specify mode: >> + 1 = low-to-high edge triggered >> + 2 = high-to-low edge triggered >> + 4 = active high level-sensitive >> + 8 = active low level-sensitive > > Just state 2 cells and refer to interrupt-controller/interrupts.txt. Thanks. I will fix it in the next version patch. >> + Default for internal sources should be set to 4 (active high). >> + >> +Examples: >> + intc: interrupt-controller { >> + compatible = "andestech,ativic32"; >> + #interrupt-cells = <2>; >> + interrupt-controller; >> + }; >> -- >> 1.7.9.5 >> From 1583504529612340794@xxx Wed Nov 08 13:26:39 +0000 2017 X-GM-THRID: 1583483451461525087 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread