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[209.132.180.67]) by mx.google.com with ESMTP id e89si3071436plb.383.2017.11.07.23.51.25; Tue, 07 Nov 2017 23:51:38 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=WCbyICWw; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754732AbdKHGW3 (ORCPT + 91 others); Wed, 8 Nov 2017 01:22:29 -0500 Received: from mail-pl0-f65.google.com ([209.85.160.65]:49536 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754403AbdKHGVF (ORCPT ); Wed, 8 Nov 2017 01:21:05 -0500 Received: by mail-pl0-f65.google.com with SMTP id f2so666910plj.6; Tue, 07 Nov 2017 22:21:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=NSrxMQNDw81kBi2X+tVji+A66q5bG3q8R7oyBufFJlQ=; b=WCbyICWwACjPjS5mF4PUzLJOj47MrYpU7fFN2qA3zczzHHaBexzXbccj85aU7Cp+ru KMgdUmZ/yh80gQwGBgkFz1J9cuoi9PGBIzzrXWdQ4BqoMFlQp/o8wukArYGPM+xhV/HN qHZBjZgpd69ad10klzUTdLZIO4GgMMDnnZEMJ6tPzBwOZxn6P+WWJFA8+yBVBNEF3FUl edX2g0BgY6iQ+UxPj7dA75O+icQSm46K5bcdB5ygccfbUFZh4fXVwXJRg0NsEYjj0w36 xEZFER8rGgBw8zqZpsdVMZdLt7EQm32wH3nR0T7Hru7ECz1tslHzN6T5brabZFa5KU0Z 9OAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=NSrxMQNDw81kBi2X+tVji+A66q5bG3q8R7oyBufFJlQ=; b=hVgzZBiajDzFYYwatYlyJrRX0gAEIERBzGX4T+NucGCatvlSR2WWlQONoEp1bQhQRu D0XLcj+CIbC4AlM4smijfCTEMHZpfoV9lrDKWpAUqhgBr/ar1xKIoehUdanBFr19TF2N iBYhIkCPcERKl34QzyTAcY6Rt2Kkp79VhZflqBYFKNNogqsaMN/FvMKlHJwifl45FKPO 5FtokhvBGMGIFhesYU3wk7YIHXpQPTlxj14VsFZtna3w2z4tXhb1Wfz/Hea0NEfP36H7 kUx3552cZmZa2VrhZvit4v8DM1oNhcWOl3LII8ay/B03bZ2cwEZ/XTSiYChoSxBgb68e zM4A== X-Gm-Message-State: AJaThX5R6sMpZ1nHDIDWgtrsoPwDJHXKzP30OBrd7299dWbDOLoPRizD Jovf8jaQP1CjQcF5yMJfu0E= X-Received: by 10.159.211.4 with SMTP id bc4mr1281430plb.160.1510122065066; Tue, 07 Nov 2017 22:21:05 -0800 (PST) Received: from app09.andestech.com ([118.163.51.199]) by smtp.gmail.com with ESMTPSA id a4sm6581339pfj.72.2017.11.07.22.21.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Nov 2017 22:21:04 -0800 (PST) From: Greentime Hu To: greentime@andestech.com, linux-kernel@vger.kernel.org, arnd@arndb.de, linux-arch@vger.kernel.org, tglx@linutronix.de, jason@lakedaemon.net, marc.zyngier@arm.com, robh+dt@kernel.org, netdev@vger.kernel.org Cc: green.hu@gmail.com, Rick Chen Subject: [PATCH 27/31] dt-bindings: interrupt-controller: Andestech Internal Vector Interrupt Controller Date: Wed, 8 Nov 2017 13:55:15 +0800 Message-Id: X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Greentime Hu Signed-off-by: Rick Chen Signed-off-by: Greentime Hu --- .../interrupt-controller/andestech,ativic32.txt | 27 ++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt new file mode 100644 index 0000000..6bac908 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/andestech,ativic32.txt @@ -0,0 +1,27 @@ +* Andestech Internal Vector Interrupt Controller + +The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller +suitable for a simpler SoC platform not requiring a more sophisticated and +bigger External Vector Interrupt Controller. + + +Main node required properties: + +- compatible : should at least contain "andestech,ativic32". +- interrupt-parent: Empty for the interrupt controller itself +- interrupt-controller : Identifies the node as an interrupt controller +- #interrupt-cells: The number of cells to define the interrupts. Should be 2. + The first cell is the IRQ number + The second cell is used to specify mode: + 1 = low-to-high edge triggered + 2 = high-to-low edge triggered + 4 = active high level-sensitive + 8 = active low level-sensitive + Default for internal sources should be set to 4 (active high). + +Examples: + intc: interrupt-controller { + compatible = "andestech,ativic32"; + #interrupt-cells = <2>; + interrupt-controller; + }; -- 1.7.9.5 From 1583480618954584265@xxx Wed Nov 08 07:06:36 +0000 2017 X-GM-THRID: 1583480618954584265 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread