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Date:   Tue, 7 Nov 2017 22:50:51 +0000
From:   James Hogan <james.hogan@mips.com>
To:     Martin Schiller <ms@dev.tdt.de>
CC:     <linux-mips@linux-mips.org>, <linux-kernel@vger.kernel.org>,
        <john@phrozen.org>, <ralf@linux-mips.org>, <hauke@hauke-m.de>,
        <arnd@arndb.de>, <nbd@nbd.name>
Subject: Re: [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks
Message-ID: <20171107225050.GM15260@jhogan-linux>
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On Tue, May 30, 2017 at 06:34:34AM +0200, Martin Schiller wrote:
> ASC1 is available on every Lantiq SoC (also AmazonSE) and should be
> enabled like the other generic xway clocks instead of ASC0, which is
> only available for AR9 and Danube.
>=20
> Signed-off-by: Martin Schiller <ms@dev.tdt.de>
> ---
>  arch/mips/lantiq/xway/sysctrl.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>=20
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysc=
trl.c
> index 95bec46..cd6dbea 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -484,9 +484,9 @@ void __init ltq_soc_init(void)
> =20
>  	/* add our generic xway clocks */
>  	clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
> -	clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
>  	clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
>  	clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
> +	clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
>  	clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
>  	clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
>  	clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
> @@ -501,7 +501,6 @@ void __init ltq_soc_init(void)
>  	}
> =20
>  	if (!of_machine_is_compatible("lantiq,ase")) {
> -		clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
>  		clkdev_add_pci();
>  	}

Thanks, applied for 4.15 (and I dropped the braces here too).

Cheers
James

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