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[209.132.180.67]) by mx.google.com with ESMTP id v187si667292pfv.227.2017.11.09.00.31.04; Thu, 09 Nov 2017 00:31:15 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=iCg9IVGH; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753528AbdKIIaU (ORCPT + 82 others); Thu, 9 Nov 2017 03:30:20 -0500 Received: from mail-pf0-f193.google.com ([209.85.192.193]:43991 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753348AbdKIIaP (ORCPT ); Thu, 9 Nov 2017 03:30:15 -0500 Received: by mail-pf0-f193.google.com with SMTP id a8so3778916pfc.0; Thu, 09 Nov 2017 00:30:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=WZsuNU/+1bQPS7W+0IvV8x6eYOLAQU0nFZKtATNd/aM=; b=iCg9IVGHUcZLIP6tFO6k0e3mYz3A/Mkw2wLK6ov4ry8aCYMx7gQG9tqDu/1NbyBzVB BU8UFHpB/GJ7cRzOmsim312XjKdg+XIkuOCopXpEt5RKbzdf0zG9US11UP30+DiGlZlI JHCi2H2IcRRohfNQjo/uRL222EBOthIBwj3SxYUWi4qXdUbS4pLiniZomJgYLteo8nWT AFJzoGXgRZbBQX3/trtPR7MW+yzLBvK62ONrcOiSdpOQ8vaI1RQZdUO3KVek+JdgPkSD 4Jni/ZPcwPNp3u39bzQpiIdIrhlGt+0yoLG5ZGhmIHhSm/oxZhZb1BevTV5siKvuVECI KJAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=WZsuNU/+1bQPS7W+0IvV8x6eYOLAQU0nFZKtATNd/aM=; b=eOPOeeZOqLSnfhyU23DvINGNJRd/MPZZ+k8ZCcW8MofTm7U3YY7nzI4GhdWSTrpIcG tnQ4n8yJ5JA1Lg1ph6j1xuCJrxmRzKrxpQ/Lau2QOCjoaD7gYasjPMosh6i712cJGnq0 rjiGzEOU/U2EdMom0P3C70zpV9u0ZrhKJOIajxZLMjMxe8qFfaIG3rWGOB3Ij00nex+K WzCoAftQIqfrKcJTtvMwdBck58N88/JNgMitUODtHGRWxP2g1ygExquMSDK/fYwjoCl0 h8+RYHqYAvjlF4WvfnSD/gmOS4oQ8yjVba3m2ZZi9GpLXO7WNkZje4JPANx8gCfZf6yS Sfog== X-Gm-Message-State: AJaThX62hTk4t/EAqxmPcJq31PoQrcyCwGbP6lrdRUPEEe2Ci6mPcvLI Si6J1h+VmraFkcudSNAmOBA= X-Received: by 10.159.246.23 with SMTP id b23mr3074409pls.60.1510216214595; Thu, 09 Nov 2017 00:30:14 -0800 (PST) Received: from app09.andestech.com ([118.163.51.199]) by smtp.gmail.com with ESMTPSA id e22sm9788488pgn.28.2017.11.09.00.30.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Nov 2017 00:30:13 -0800 (PST) From: Rick Chen To: daniel.lezcano@linaro.org, tglx@linutronix.de, robh@kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, rick@andestech.com Cc: Rick Chen , Greentime Hu Subject: [PATCH v4 3/3] dt-bindings: timer: Add andestech atcpit100 timer binding doc Date: Thu, 9 Nov 2017 16:05:28 +0800 Message-Id: <1510214728-22441-4-git-send-email-rickchen36@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1510214728-22441-1-git-send-email-rickchen36@gmail.com> References: <1510214728-22441-1-git-send-email-rickchen36@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a document to describe Andestech atcpit100 timer and binding information. Signed-off-by: Rick Chen Acked-by: Rob Herring Signed-off-by: Greentime Hu --- .../bindings/timer/andestech,atcpit100-timer.txt | 33 ++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt diff --git a/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt new file mode 100644 index 0000000..b97ff32 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/andestech,atcpit100-timer.txt @@ -0,0 +1,33 @@ +Andestech ATCPIT100 timer +------------------------------------------------------------------ +ATCPIT100 is a generic IP block from Andes Technology, embedded in +Andestech AE3XX platforms and other designs. + +This timer is a set of compact multi-function timers, which can be +used as pulse width modulators (PWM) as well as simple timers. + +It supports up to 4 PIT channels. Each PIT channel is a +multi-function timer and provide the following usage scenarios: +One 32-bit timer +Two 16-bit timers +Four 8-bit timers +One 16-bit PWM +One 16-bit timer and one 8-bit PWM +Two 8-bit timer and one 8-bit PWM + +Required properties: +- compatible : Should be "andestech,atcpit100" +- reg : Address and length of the register set +- interrupts : Reference to the timer interrupt +- clocks : a clock to provide the tick rate for "andestech,atcpit100" +- clock-names : should be "PCLK" for the external tick timer. + +Examples: + +timer0: timer@f0400000 { + compatible = "andestech,atcpit100"; + reg = <0xf0400000 0x1000>; + interrupts = <2 4>; + clocks = <&clk_pll>; + clock-names = "PCLK"; +}; -- 2.7.4 From 1586267649837795879@xxx Sat Dec 09 01:25:16 +0000 2017 X-GM-THRID: 1586254538865552192 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread