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[209.132.180.67]) by mx.google.com with ESMTP id l3si12371708pff.82.2017.11.06.09.28.42; Mon, 06 Nov 2017 09:28:55 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754536AbdKFRE2 (ORCPT + 96 others); Mon, 6 Nov 2017 12:04:28 -0500 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:52287 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754520AbdKFRE0 (ORCPT ); Mon, 6 Nov 2017 12:04:26 -0500 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vA6Gx43d020601; Mon, 6 Nov 2017 18:03:45 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2e15ahkq2y-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 06 Nov 2017 18:03:45 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9FA2C31; Mon, 6 Nov 2017 17:03:42 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5219828BF; Mon, 6 Nov 2017 17:03:42 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.46) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.352.0; Mon, 6 Nov 2017 18:03:42 +0100 Received: from lmecxl0923.lme.st.com (10.48.0.237) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.352.0; Mon, 6 Nov 2017 18:03:41 +0100 From: Ludovic Barre To: Thomas Gleixner , Jason Cooper , Marc Zyngier , Rob Herring CC: Maxime Coquelin , Alexandre Torgue , , , Subject: [PATCH v3 0/9] irqchip: stm32: add stm32h7 support Date: Mon, 6 Nov 2017 18:03:30 +0100 Message-ID: <1509987819-29599-1-git-send-email-ludovic.Barre@st.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.48.0.237] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2017-11-06_06:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ludovic Barre This series adds: -Management of multi-bank of external interrupts stm32h7 has up to 96 inputs (3 banks of 32 inputs). -Fix initial value after cold/hot boot (wakeup issue). Changes v3: -remove chip.name and handler, already done by irq_alloc_domain_generic_chips -add Rob ack in dt-bindings commit Changes v2: -Remove irq_mask and adds const on struct stm32_exti_bank -Add wrapper functions pending and ack -Replace BITS_PER_LONG by IRQS_PER_BANK -Fill commit message on "ARM: dts: stm32: add support of exti on stm32h743" -Add system config bank for stm32h7 Ludovic Barre (9): irqchip: stm32: select GENERIC_IRQ_CHIP irqchip: stm32: add multi-bank management dt-bindings: interrupt-controllers: add compatible string for stm32h7 irqchip: stm32: add stm32h7 support irqchip: stm32: fix initial values irqchip: stm32: move the wakeup on interrupt mask ARM: dts: stm32: add exti support for stm32h743 ARM: dts: stm32: add system config bank node for stm32h743 ARM: dts: stm32: add support of exti on stm32h743 pinctrl .../interrupt-controller/st,stm32-exti.txt | 4 +- arch/arm/boot/dts/stm32h743-pinctrl.dtsi | 24 +++ arch/arm/boot/dts/stm32h743.dtsi | 13 ++ drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-stm32-exti.c | 206 ++++++++++++++++----- 5 files changed, 198 insertions(+), 50 deletions(-) -- 2.7.4 From 1583338358922479186@xxx Mon Nov 06 17:25:27 +0000 2017 X-GM-THRID: 1583338358922479186 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread