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[209.132.180.67]) by mx.google.com with ESMTP id 61si3616355plz.155.2017.11.02.20.29.59; Thu, 02 Nov 2017 20:30:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=UfiBrDWA; dkim=pass header.i=@codeaurora.org header.s=default header.b=jrDXGLmu; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965103AbdKCD2t (ORCPT + 97 others); Thu, 2 Nov 2017 23:28:49 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49150 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934752AbdKCD2N (ORCPT ); Thu, 2 Nov 2017 23:28:13 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 29B64607CF; Fri, 3 Nov 2017 03:28:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509679693; bh=40RXlds3k4X2gsDTXmoH8pa2UNPW1bbDEElOUFQgS7I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UfiBrDWArQjf2MdP7L9SKlcrfGOLdANzhBNSiFqW8HNX5gb+8ylOn1cnZaKhsoOq4 +x5gkK7jgaF4AaOwGGK4FZyt4mqgpm9iKxbohRz0XOqRqQA5D/IhV8JXWw+785PygV aVVX1881VukpNnPj8bieNStuHQ0ja2MvuLrtLid8= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from shankerd-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: shankerd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 6E8EE606B7; Fri, 3 Nov 2017 03:28:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509679692; bh=40RXlds3k4X2gsDTXmoH8pa2UNPW1bbDEElOUFQgS7I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jrDXGLmuWxtduJxjdj/7T4dF2OINdnFxqT9aIIcxE4sXc2BGkMh3Wrgch9jL40g0X IEcy7WXUmrObA+YzNOBehe91F2vFJVfB+8fmzO9aYHvZl3royr3tdLJmlZLAr6GajT Dr2GkP+cljcmnY38oDpjq1Q8reJPLYZqo/pRGiSg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 6E8EE606B7 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org From: Shanker Donthineni To: Will Deacon , Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Ard Biesheuvel , Matt Fleming , Christoffer Dall , linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Shanker Donthineni , Neil Leeder Subject: [PATCH 1/3] arm64: Define cputype macros for Falkor CPU Date: Thu, 2 Nov 2017 22:27:42 -0500 Message-Id: <1509679664-3749-2-git-send-email-shankerd@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1509679664-3749-1-git-send-email-shankerd@codeaurora.org> References: <1509679664-3749-1-git-send-email-shankerd@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add cputype definition macros for Qualcomm Datacenter Technologies Falkor CPU in cputype.h. It's unfortunate that the first revision of the Falkor CPU used the wrong part number 0x800, got fixed in v2 chip with part number 0xC00, and would be used the same value for future revisions. Signed-off-by: Shanker Donthineni Signed-off-by: Neil Leeder --- arch/arm64/include/asm/cputype.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 235e77d..cbf08d7 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -91,6 +91,7 @@ #define BRCM_CPU_PART_VULCAN 0x516 #define QCOM_CPU_PART_FALKOR_V1 0x800 +#define QCOM_CPU_PART_FALKOR 0xC00 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) @@ -99,6 +100,7 @@ #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) +#define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) #ifndef __ASSEMBLY__ -- Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. From 1583032294357577259@xxx Fri Nov 03 08:20:41 +0000 2017 X-GM-THRID: 1581775102950037022 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread