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[61.45.92.183]) by smtp.gmail.com with ESMTPSA id n12sm9110103pfb.149.2017.11.02.22.04.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Nov 2017 22:04:43 -0700 (PDT) Date: Fri, 3 Nov 2017 14:04:42 +0900 From: Stafford Horne To: LKML Cc: Openrisc , Rob Herring , Mark Rutland , "David S. Miller" , Greg Kroah-Hartman , Mauro Carvalho Chehab , Randy Dunlap , devicetree@vger.kernel.org Subject: Re: [PATCH 3/3] openrisc: dts: Add OpenRISC platform SoC Message-ID: <20171103050442.GJ29237@lianli.shorne-pla.net> References: <20171022024641.28478-1-shorne@gmail.com> <20171022024641.28478-4-shorne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20171022024641.28478-4-shorne@gmail.com> User-Agent: Mutt/1.9.1 (2017-09-22) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sun, Oct 22, 2017 at 11:46:41AM +0900, Stafford Horne wrote: > Add devicetree binding documentation for the OpenRISC platform > opencores,or1ksim. This is the main OpenRISC reference platform > supporting multiple FPGA SoC's. > > This format is based on some of the mips binding docs as we have > similar requirements. > > Also, update maintainers so openrisc related binding changes are visible > to the openrisc team. > [..] > diff --git a/MAINTAINERS b/MAINTAINERS > index a57d13cb414d..71e4f6762196 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -10008,6 +10008,7 @@ T: git git://github.com/openrisc/linux.git > L: openrisc@lists.librecores.org > W: http://openrisc.io > S: Maintained > +F; Documentation/devicetree/bindings/openrisc/ FYI, I found this typo (; vs :) which I have fixed and am pushing to next. > F: Documentation/openrisc/ > F: arch/openrisc/ > F: drivers/irqchip/irq-or1k-* > -- > 2.13.6 > From 1582591670334837140@xxx Sun Oct 29 11:37:09 +0000 2017 X-GM-THRID: 1581924306857859313 X-Gmail-Labels: Inbox,Category Forums