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[209.132.180.67]) by mx.google.com with ESMTP id m85si5571546pfa.287.2017.11.02.20.28.50; Thu, 02 Nov 2017 20:29:05 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@codeaurora.org header.s=default header.b=fsbNfxpz; dkim=pass header.i=@codeaurora.org header.s=default header.b=fsbNfxpz; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934774AbdKCD2O (ORCPT + 97 others); Thu, 2 Nov 2017 23:28:14 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:49044 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932734AbdKCD2M (ORCPT ); Thu, 2 Nov 2017 23:28:12 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id CCE586079E; Fri, 3 Nov 2017 03:28:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509679691; bh=2WDysy07E0dGO3eMH08UqH3m3bTSR6qzKNOON8V07Fs=; h=From:To:Cc:Subject:Date:From; b=fsbNfxpzbqyxWzVNC8vfJN7POHnpLYU7c1FSbovnQ42XmAdATr8xMMyib/39+Wau+ lI3iYUa5a5tMDRpdTJHmz/IWEv/+mSjT7HCZhDX5FYVYfuxnAkQ4Gd0fvtNOwXUHNf HW+eiCc8JAGaQPWCAqSiimdT2zHFlC38AyPXyLBo= X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on pdx-caf-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00, DKIM_SIGNED,T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from shankerd-ubuntu.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: shankerd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 4A215600CE; Fri, 3 Nov 2017 03:28:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1509679691; bh=2WDysy07E0dGO3eMH08UqH3m3bTSR6qzKNOON8V07Fs=; h=From:To:Cc:Subject:Date:From; b=fsbNfxpzbqyxWzVNC8vfJN7POHnpLYU7c1FSbovnQ42XmAdATr8xMMyib/39+Wau+ lI3iYUa5a5tMDRpdTJHmz/IWEv/+mSjT7HCZhDX5FYVYfuxnAkQ4Gd0fvtNOwXUHNf HW+eiCc8JAGaQPWCAqSiimdT2zHFlC38AyPXyLBo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 4A215600CE Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=shankerd@codeaurora.org From: Shanker Donthineni To: Will Deacon , Marc Zyngier , linux-arm-kernel@lists.infradead.org Cc: Catalin Marinas , Ard Biesheuvel , Matt Fleming , Christoffer Dall , linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, kvmarm@lists.cs.columbia.edu, Shanker Donthineni Subject: [PATCH 0/3] Implement a software workaround for Falkor erratum 1041 Date: Thu, 2 Nov 2017 22:27:41 -0500 Message-Id: <1509679664-3749-1-git-send-email-shankerd@codeaurora.org> X-Mailer: git-send-email 1.9.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Falkor CPU, we’ve discovered a hardware issue which might lead to a kernel crash or the unexpected behavior. The Falkor core may errantly access memory locations on speculative instruction fetches. This may happen whenever MMU translation state, SCTLR_ELn[M] bit is being changed from enabled to disabled for the currently running exception level. To prevent the errant hardware behavior, software must execute an ISB immediately prior to executing the MSR that changes SCTLR_ELn[M] from a value of 1 to 0. To simplify the complexity of a workaround, this patch series issues an ISB whenever SCTLR_ELn[M] is changed to 0 to fix the Falkor erratum 1041. Patch1: - CPUTYPE definitions for Falkor CPU. Patch2: - Define two ASM helper macros to read/write SCTLR_ELn register. Patch3: - Actual workaround changes for erratum E1041. Shanker Donthineni (3): arm64: Define cputype macros for Falkor CPU arm64: Prepare SCTLR_ELn accesses to handle Falkor erratum 1041 arm64: Add software workaround for Falkor erratum 1041 Documentation/arm64/silicon-errata.txt | 1 + arch/arm64/Kconfig | 10 ++++++++++ arch/arm64/include/asm/assembler.h | 35 ++++++++++++++++++++++++++++++++++ arch/arm64/include/asm/cpucaps.h | 3 ++- arch/arm64/include/asm/cputype.h | 2 ++ arch/arm64/kernel/cpu-reset.S | 4 ++-- arch/arm64/kernel/cpu_errata.c | 16 ++++++++++++++++ arch/arm64/kernel/efi-entry.S | 8 ++++---- arch/arm64/kernel/head.S | 18 ++++++++--------- arch/arm64/kernel/relocate_kernel.S | 4 ++-- arch/arm64/kvm/hyp-init.S | 6 +++--- arch/arm64/mm/proc.S | 6 +++--- 12 files changed, 89 insertions(+), 24 deletions(-) -- Qualcomm Datacenter Technologies, Inc. on behalf of the Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. 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