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[209.132.180.67]) by mx.google.com with ESMTP id y70si3935792pfg.300.2017.11.02.06.52.49; Thu, 02 Nov 2017 06:53:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755747AbdKBNwI convert rfc822-to-8bit (ORCPT + 96 others); Thu, 2 Nov 2017 09:52:08 -0400 Received: from mga06.intel.com ([134.134.136.31]:18885 "EHLO mga06.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755713AbdKBNwE (ORCPT ); Thu, 2 Nov 2017 09:52:04 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP; 02 Nov 2017 06:52:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,334,1505804400"; d="scan'208";a="916710995" Received: from fmsmsx107.amr.corp.intel.com ([10.18.124.205]) by FMSMGA003.fm.intel.com with ESMTP; 02 Nov 2017 06:51:59 -0700 Received: from fmsmsx102.amr.corp.intel.com (10.18.124.200) by fmsmsx107.amr.corp.intel.com (10.18.124.205) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 2 Nov 2017 06:51:59 -0700 Received: from shsmsx102.ccr.corp.intel.com (10.239.4.154) by FMSMSX102.amr.corp.intel.com (10.18.124.200) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 2 Nov 2017 06:51:59 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.213]) by shsmsx102.ccr.corp.intel.com ([169.254.2.175]) with mapi id 14.03.0319.002; Thu, 2 Nov 2017 21:51:58 +0800 From: "Liang, Kan" To: Thomas Gleixner CC: "peterz@infradead.org" , "mingo@redhat.com" , "linux-kernel@vger.kernel.org" , "acme@kernel.org" , "eranian@google.com" , "ak@linux.intel.com" Subject: RE: [PATCH V3 1/5] perf/x86/intel/uncore: customized pmu event read for client IMC uncore Thread-Topic: [PATCH V3 1/5] perf/x86/intel/uncore: customized pmu event read for client IMC uncore Thread-Index: AQHTTPn8N2Thg1PlBU23gMJh7UBtUqMAoguAgACGaBA= Date: Thu, 2 Nov 2017 13:51:58 +0000 Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077537DCA04@SHSMSX103.ccr.corp.intel.com> References: <1508843124-4081-1-git-send-email-kan.liang@intel.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYWI2ZTJjMzUtNDViMC00MmMzLTliYjEtZmM4NDYwZWUxNGVhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE2LjUuOS4zIiwiVHJ1c3RlZExhYmVsSGFzaCI6InZNSkhweWVcL0dLMkxoTm5hWUg2YzlBbXhpVVNLaFAxcWF0RzM0clIzcEZNPSJ9 x-ctpclassification: CTP_IC dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > On Tue, 24 Oct 2017, kan.liang@intel.com wrote: > > - if (event->hw.idx >= UNCORE_PMC_IDX_FIXED) > > + if (event->hw.idx == UNCORE_PMC_IDX_FIXED) > > shift = 64 - uncore_fixed_ctr_bits(box); > > else > > shift = 64 - uncore_perf_ctr_bits(box); diff --git > > a/arch/x86/events/intel/uncore_snb.c > > b/arch/x86/events/intel/uncore_snb.c > > index db1127c..9d5cd3f 100644 > > --- a/arch/x86/events/intel/uncore_snb.c > > +++ b/arch/x86/events/intel/uncore_snb.c > > @@ -498,6 +498,30 @@ static void snb_uncore_imc_event_del(struct > perf_event *event, int flags) > > snb_uncore_imc_event_stop(event, PERF_EF_UPDATE); } > > > > +static void snb_uncore_imc_event_read(struct perf_event *event) { > > + struct intel_uncore_box *box = uncore_event_to_box(event); > > + u64 prev_count, new_count, delta; > > + int shift; > > + > > + if (event->hw.idx >= UNCORE_PMC_IDX_FIXED) > > And this needs to be >= because? Patch 5/5 will clean up the client IMC uncore. Before that, we still need it to make client IMC uncore work. This patch isolates the >= case for client IMC uncore. Thanks, Kan From 1582962309734866726@xxx Thu Nov 02 13:48:18 +0000 2017 X-GM-THRID: 1582166476632080836 X-Gmail-Labels: Inbox,Category Forums,HistoricalUnread