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From:   Wanpeng Li <kernellwp@gmail.com>
Date:   Fri, 3 Nov 2017 08:55:00 +0800
Message-ID: <CANRm+CwqhA44nqZDwAs0e-DA=fDZLu7JTR2EbG9kYPVeFXFOZw@mail.gmail.com>
Subject: Re: [PATCH v3 1/3] KVM: X86: Fix operand size during instruction decoding
To:     Paolo Bonzini <pbonzini@redhat.com>
Cc:     "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        kvm <kvm@vger.kernel.org>,
        =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= <rkrcmar@redhat.com>,
        Wanpeng Li <wanpeng.li@hotmail.com>,
        Nadav Amit <nadav.amit@gmail.com>,
        Pedro Fonseca <pfonseca@cs.washington.edu>
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2017-11-03 1:45 GMT+08:00 Paolo Bonzini <pbonzini@redhat.com>:
> On 02/11/2017 09:31, Wanpeng Li wrote:
>> From: Wanpeng Li <wanpeng.li@hotmail.com>
>>
>> Pedro reported:
>>   During tests that we conducted on KVM, we noticed that executing a "PU=
SH %ES"
>>   instruction under KVM produces different results on both memory and th=
e SP
>>   register depending on whether EPT support is enabled. With EPT the SP =
is
>>   reduced by 4 bytes (and the written value is 0-padded) but without EPT=
 support
>>   it is only reduced by 2 bytes. The difference can be observed when the=
 CS.DB
>>   field is 1 (32-bit) but not when it's 0 (16-bit).
>>
>> The internal segment descriptor cache exist even in real/vm8096 mode. Th=
e CS.D
>> also should be respected instead of just default operand-size/66H prefix=
 during
>> instruction decoding. This patch fixes it by also adjusting operand-size=
 according
>> to CS.D.
>>
>> Reported-by: Pedro Fonseca <pfonseca@cs.washington.edu>
>> Tested-by: Pedro Fonseca <pfonseca@cs.washington.edu>
>> Cc: Paolo Bonzini <pbonzini@redhat.com>
>> Cc: Radim Kr=C4=8Dm=C3=A1=C5=99 <rkrcmar@redhat.com>
>> Cc: Nadav Amit <nadav.amit@gmail.com>
>> Cc: Pedro Fonseca <pfonseca@cs.washington.edu>
>> Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com>
>> ---
>> v2 -> v3:
>>  * cleanup the codes
>> v1 -> v2:
>>  * respect cs.d for real/vm8096, other modes have already
>>    been considered in init_emulate_ctxt().
>>
>>  arch/x86/kvm/emulate.c | 7 +++++++
>>  1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
>> index 8079d14..6ebc4cb 100644
>> --- a/arch/x86/kvm/emulate.c
>> +++ b/arch/x86/kvm/emulate.c
>> @@ -5000,6 +5000,8 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt,=
 void *insn, int insn_len)
>>       bool op_prefix =3D false;
>>       bool has_seg_override =3D false;
>>       struct opcode opcode;
>> +     u16 dummy;
>> +     struct desc_struct desc;
>>
>>       ctxt->memop.type =3D OP_NONE;
>>       ctxt->memopp =3D NULL;
>> @@ -5020,6 +5022,11 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt=
, void *insn, int insn_len)
>>       case X86EMUL_MODE_VM86:
>>       case X86EMUL_MODE_PROT16:
>>               def_op_bytes =3D def_ad_bytes =3D 2;
>> +             if (mode < X86EMUL_MODE_PROT16) {
>> +                     ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, =
VCPU_SREG_CS);
>> +                     if (desc.d)
>> +                             def_op_bytes =3D 4;
>
> def_ad_bytes must be changed to 4 as well.  With that change, you should
> probably separate X86EMUL_MODE_PROT16 altogether from the others.

I just handle all the comments of the three patches in v5. :)

Regards,
Wanpeng Li

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