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From:   Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
To:     linux-snps-arc@lists.infradead.org
Cc:     linux-kernel@vger.kernel.org,
        Vineet Gupta <Vineet.Gupta1@synopsys.com>,
        Alexey Brodkin <Alexey.Brodkin@synopsys.com>,
        Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Subject: [PATCH 0/4] ARC: Set initial core pll output frequency via DTS
Date:   Mon, 27 Nov 2017 21:56:07 +0300
Message-Id: <20171127185611.12379-1-Eugeniy.Paltsev@synopsys.com>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.  
It will be applied at the core pll driver probing.

Eugeniy Paltsev (4):
  ARC: [plat-hsdk]: Set initial core pll output frequency
  ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
  ARC: [plat-axs103]: Set initial core pll output frequency
  ARC: [plat-axs103] refactor the quad core DT quirk code

 arch/arc/boot/dts/axc003.dtsi     |  3 +++
 arch/arc/boot/dts/axc003_idu.dtsi |  3 +++
 arch/arc/boot/dts/hsdk.dts        |  3 +++
 arch/arc/plat-axs10x/axs10x.c     | 18 ++++++++---------
 arch/arc/plat-hsdk/platform.c     | 42 ---------------------------------------
 5 files changed, 17 insertions(+), 52 deletions(-)

-- 
2.9.3


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