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From: Ian Rogers <irogers@google.com>
Date: Mon, 25 Mar 2024 07:34:23 -0700
Message-ID: <CAP-5=fVLWMnT4TV2nvbOUTTkWHYowbEOFDYqAvf1hkUEDpkKfw@mail.gmail.com>
Subject: Re: [PATCH 1/2] perf/x86/amd/core: Update stalled-cycles-* events for
 Zen 2 and later
To: Sandipan Das <sandipan.das@amd.com>
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, 
	x86@kernel.org, peterz@infradead.org, mingo@kernel.org, acme@kernel.org, 
	namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, 
	jolsa@kernel.org, adrian.hunter@intel.com, tglx@linutronix.de, bp@alien8.de, 
	eranian@google.com, ravi.bangoria@amd.com, ananth.narayan@amd.com
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On Mon, Mar 25, 2024 at 12:48=E2=80=AFAM Sandipan Das <sandipan.das@amd.com=
> wrote:
>
> AMD processors based on Zen 2 and later microarchitectures do not
> support PMCx087 (instruction pipe stalls) which is used as the backing
> event for "stalled-cycles-frontend" and "stalled-cycles-backend". Use
> PMCx0A9 (cycles where micro-op queue is empty) instead to count frontend
> stalls and remove the entry for backend stalls since there is no direct
> replacement.
>
> Signed-off-by: Sandipan Das <sandipan.das@amd.com>

This looks good to me. Should there be a Fixes tag for the sake of backport=
s?

Reviewed-by: Ian Rogers <irogers@google.com>

Thanks,
Ian

> ---
>  arch/x86/events/amd/core.c | 20 +++++++++++++++++---
>  1 file changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index aec16e581f5b..afe4a809f2ed 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_=
MAX] =3D
>  /*
>   * AMD Performance Monitor Family 17h and later:
>   */
> -static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =3D
> +static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =3D
>  {
>         [PERF_COUNT_HW_CPU_CYCLES]              =3D 0x0076,
>         [PERF_COUNT_HW_INSTRUCTIONS]            =3D 0x00c0,
> @@ -262,10 +262,24 @@ static const u64 amd_f17h_perfmon_event_map[PERF_CO=
UNT_HW_MAX] =3D
>         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  =3D 0x0187,
>  };
>
> +static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =3D
> +{
> +       [PERF_COUNT_HW_CPU_CYCLES]              =3D 0x0076,
> +       [PERF_COUNT_HW_INSTRUCTIONS]            =3D 0x00c0,
> +       [PERF_COUNT_HW_CACHE_REFERENCES]        =3D 0xff60,
> +       [PERF_COUNT_HW_CACHE_MISSES]            =3D 0x0964,
> +       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     =3D 0x00c2,
> +       [PERF_COUNT_HW_BRANCH_MISSES]           =3D 0x00c3,
> +       [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =3D 0x00a9,
> +};
> +
>  static u64 amd_pmu_event_map(int hw_event)
>  {
> -       if (boot_cpu_data.x86 >=3D 0x17)
> -               return amd_f17h_perfmon_event_map[hw_event];
> +       if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >=
=3D 0x19)
> +               return amd_zen2_perfmon_event_map[hw_event];
> +
> +       if (cpu_feature_enabled(X86_FEATURE_ZEN1))
> +               return amd_zen1_perfmon_event_map[hw_event];
>
>         return amd_perfmon_event_map[hw_event];
>  }
> --
> 2.34.1
>