Received-SPF: pass (google.com: domain of linux-kernel+bounces-117349-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223;
Precedence: bulk
MIME-Version: 1.0
References: <20231129093113.255161-1-paul.elder@ideasonboard.com>
 <20231129093113.255161-2-paul.elder@ideasonboard.com> <CAHCN7xLOu5qfxNihEYuSXxuxxH=S_+7nDkX1H=ziDW3QvaErQA@mail.gmail.com>
 <20240325151402.GW18799@pendragon.ideasonboard.com>
In-Reply-To: <20240325151402.GW18799@pendragon.ideasonboard.com>
From: Adam Ford <aford173@gmail.com>
Date: Mon, 25 Mar 2024 10:17:21 -0500
Message-ID: <CAHCN7xKczvZzQYGKeEC4Z7-2wWDa2FijugW1_HcayVOLg7D38A@mail.gmail.com>
Subject: Re: [PATCH 1/2] arm64: dts: imx8mp: Add DT nodes for the two ISPs
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Paul Elder <paul.elder@ideasonboard.com>, linux-media@vger.kernel.org, 
	devicetree@vger.kernel.org, kieran.bingham@ideasonboard.com, 
	tomi.valkeinen@ideasonboard.com, umang.jain@ideasonboard.com, 
	Rob Herring <robh+dt@kernel.org>, 
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Conor Dooley <conor+dt@kernel.org>, 
	Shawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>, 
	Pengutronix Kernel Team <kernel@pengutronix.de>, Fabio Estevam <festevam@gmail.com>, 
	NXP Linux Team <linux-imx@nxp.com>, Marek Vasut <marex@denx.de>, 
	Alexander Stein <alexander.stein@ew.tq-group.com>, Lucas Stach <l.stach@pengutronix.de>, 
	Frank Li <Frank.Li@nxp.com>, 
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" <linux-arm-kernel@lists.infradead.org>, 
	open list <linux-kernel@vger.kernel.org>
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable

On Mon, Mar 25, 2024 at 10:14=E2=80=AFAM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> Hi Adam,
>
> On Wed, Mar 20, 2024 at 07:35:46AM -0500, Adam Ford wrote:
> > On Wed, Nov 29, 2023 at 3:31=E2=80=AFAM Paul Elder wrote:
> > >
> > > The ISP supports both CSI and parallel interfaces, where port 0
> > > corresponds to the former and port 1 corresponds to the latter. Since
> > > the i.MX8MP's ISPs are connected by the parallel interface to the CSI
> > > receiver, set them both to port 1.
> > >
> > > Signed-off-by: Paul Elder <paul.elder@ideasonboard.com>
> >
> > Paul, are you able to resend this now that the driver part has been
> > merged into the main branch?
> >
> > If you can't, I can resend it on your behalf.
>
> I've just sent a v2, you're on CC.

Thanks!

adam
>
> > > ---
> > >  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 50 +++++++++++++++++++++=
++
> > >  1 file changed, 50 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/b=
oot/dts/freescale/imx8mp.dtsi
> > > index c9a610ba4836..25579d4c58f2 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -1604,6 +1604,56 @@ isi_in_1: endpoint {
> > >                                 };
> > >                         };
> > >
> > > +                       isp_0: isp@32e10000 {
> > > +                               compatible =3D "fsl,imx8mp-isp";
> > > +                               reg =3D <0x32e10000 0x10000>;
> > > +                               interrupts =3D <GIC_SPI 74 IRQ_TYPE_L=
EVEL_HIGH>;
> > > +                               clocks =3D <&clk IMX8MP_CLK_MEDIA_ISP=
_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_AXI_R=
OOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_APB_R=
OOT>;
> > > +                               clock-names =3D "isp", "aclk", "hclk"=
;
> > > +                               assigned-clocks =3D <&clk IMX8MP_CLK_=
MEDIA_ISP>;
> > > +                               assigned-clock-parents =3D <&clk IMX8=
MP_SYS_PLL2_500M>;
> > > +                               assigned-clock-rates =3D <500000000>;
> > > +                               power-domains =3D <&media_blk_ctrl IM=
X8MP_MEDIABLK_PD_ISP>;
> > > +                               fsl,blk-ctrl =3D <&media_blk_ctrl 0>;
> > > +                               status =3D "disabled";
> > > +
> > > +                               ports {
> > > +                                       #address-cells =3D <1>;
> > > +                                       #size-cells =3D <0>;
> > > +
> > > +                                       port@1 {
> > > +                                               reg =3D <1>;
> > > +                                       };
> > > +                               };
> > > +                       };
> > > +
> > > +                       isp_1: isp@32e20000 {
> > > +                               compatible =3D "fsl,imx8mp-isp";
> > > +                               reg =3D <0x32e20000 0x10000>;
> > > +                               interrupts =3D <GIC_SPI 75 IRQ_TYPE_L=
EVEL_HIGH>;
> > > +                               clocks =3D <&clk IMX8MP_CLK_MEDIA_ISP=
_ROOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_AXI_R=
OOT>,
> > > +                                        <&clk IMX8MP_CLK_MEDIA_APB_R=
OOT>;
> > > +                               clock-names =3D "isp", "aclk", "hclk"=
;
> > > +                               assigned-clocks =3D <&clk IMX8MP_CLK_=
MEDIA_ISP>;
> > > +                               assigned-clock-parents =3D <&clk IMX8=
MP_SYS_PLL2_500M>;
> > > +                               assigned-clock-rates =3D <500000000>;
> > > +                               power-domains =3D <&media_blk_ctrl IM=
X8MP_MEDIABLK_PD_ISP>;
> > > +                               fsl,blk-ctrl =3D <&media_blk_ctrl 1>;
> > > +                               status =3D "disabled";
> > > +
> > > +                               ports {
> > > +                                       #address-cells =3D <1>;
> > > +                                       #size-cells =3D <0>;
> > > +
> > > +                                       port@1 {
> > > +                                               reg =3D <1>;
> > > +                                       };
> > > +                               };
> > > +                       };
> > > +
> > >                         dewarp: dwe@32e30000 {
> > >                                 compatible =3D "nxp,imx8mp-dw100";
> > >                                 reg =3D <0x32e30000 0x10000>;
>
> --
> Regards,
>
> Laurent Pinchart