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From: Ian Rogers <irogers@google.com>
Date: Mon, 25 Mar 2024 07:43:46 -0700
Message-ID: <CAP-5=fVFh8rN24JnUUGx2DjYBSY6HCHi00tvC3=HBow3oTpMbw@mail.gmail.com>
Subject: Re: [PATCH 2/2] perf/x86/amd/core: Add ref-cycles event for Zen 4 and later
To: Sandipan Das <sandipan.das@amd.com>
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, 
	x86@kernel.org, peterz@infradead.org, mingo@kernel.org, acme@kernel.org, 
	namhyung@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, 
	jolsa@kernel.org, adrian.hunter@intel.com, tglx@linutronix.de, bp@alien8.de, 
	eranian@google.com, ravi.bangoria@amd.com, ananth.narayan@amd.com
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On Mon, Mar 25, 2024 at 12:48=E2=80=AFAM Sandipan Das <sandipan.das@amd.com=
> wrote:
>
> Add the "ref-cycles" event for AMD processors based on Zen 4 and later
> microarchitectures. The backing event is based on PMCx120 which counts
> cycles not in halt state in P0 frequency (same as MPERF).

This reminds me that we lack smi cost and an smi_cycles metric for
AMD, here is an Intel one:
https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tr=
ee/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json?h=3Dperf-tools-=
next#n274
The metric uses APERF but runs with freeze_on_smi set:
https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tr=
ee/tools/perf/builtin-stat.c?h=3Dperf-tools-next#n2115
so the delta between cycles and aperf is the cycles in SMI. It would
be great if we could get something similar on AMD.

> Signed-off-by: Sandipan Das <sandipan.das@amd.com>

Reviewed-by: Ian Rogers <irogers@google.com>

Thanks,
Ian

> ---
>  arch/x86/events/amd/core.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
> index afe4a809f2ed..685bfa860d67 100644
> --- a/arch/x86/events/amd/core.c
> +++ b/arch/x86/events/amd/core.c
> @@ -273,8 +273,23 @@ static const u64 amd_zen2_perfmon_event_map[PERF_COU=
NT_HW_MAX] =3D
>         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =3D 0x00a9,
>  };
>
> +static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =3D
> +{
> +       [PERF_COUNT_HW_CPU_CYCLES]              =3D 0x0076,
> +       [PERF_COUNT_HW_INSTRUCTIONS]            =3D 0x00c0,
> +       [PERF_COUNT_HW_CACHE_REFERENCES]        =3D 0xff60,
> +       [PERF_COUNT_HW_CACHE_MISSES]            =3D 0x0964,
> +       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     =3D 0x00c2,
> +       [PERF_COUNT_HW_BRANCH_MISSES]           =3D 0x00c3,
> +       [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =3D 0x00a9,
> +       [PERF_COUNT_HW_REF_CPU_CYCLES]          =3D 0x100000120,
> +};
> +
>  static u64 amd_pmu_event_map(int hw_event)
>  {
> +       if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >=
=3D 0x1a)
> +               return amd_zen4_perfmon_event_map[hw_event];
> +
>         if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >=
=3D 0x19)
>                 return amd_zen2_perfmon_event_map[hw_event];
>
> --
> 2.34.1
>