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From: Peng Fan <peng.fan@nxp.com>
To: Thomas Gleixner <tglx@linutronix.de>, "Peng Fan (OSS)"
	<peng.fan@oss.nxp.com>, Will Deacon <will@kernel.org>, Robin Murphy
	<robin.murphy@arm.com>, Joerg Roedel <joro@8bytes.org>, Marc Zyngier
	<maz@kernel.org>
CC: Bixuan Cui <cuibixuan@huawei.com>, "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>, "iommu@lists.linux.dev"
	<iommu@lists.linux.dev>, "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 2/3] genirq/msi: cache the last msi msg
Thread-Topic: [PATCH 2/3] genirq/msi: cache the last msi msg
Thread-Index: AQHafeW34dOiKtZ0j0mwPH9MiAa2yLFIu2UAgAB4hmA=
Date: Tue, 26 Mar 2024 01:02:09 +0000
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References: <20240324-smmu-v3-v1-0-11bc96e156a5@nxp.com>
 <20240324-smmu-v3-v1-2-11bc96e156a5@nxp.com> <878r26fbv9.ffs@tglx>
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> Subject: Re: [PATCH 2/3] genirq/msi: cache the last msi msg
>=20
> On Sun, Mar 24 2024 at 20:28, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > Cache the last msi msg which will be used for ARM SMMU V3 resume
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > ---
> >  kernel/irq/msi.c | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/kernel/irq/msi.c b/kernel/irq/msi.c index
> > f90952ebc494..9d7e0a675089 100644
> > --- a/kernel/irq/msi.c
> > +++ b/kernel/irq/msi.c
> > @@ -617,6 +617,9 @@ static unsigned int msi_domain_get_hwsize(struct
> > device *dev, unsigned int domid  static inline void
> irq_chip_write_msi_msg(struct irq_data *data,
> >  					  struct msi_msg *msg)
> >  {
> > +	struct msi_desc *desc =3D irq_data_get_msi_desc(data);
> > +
> > +	desc->msg =3D *msg;
> >  	data->chip->irq_write_msi_msg(data, msg);  }
>=20
> This should remove the very same line in the PCI/MSI code, no?

I think no, but you have more knowledge than me, please correct if I am
wrong.
To zpci_irq_chip.irq_set_affinity
  zpci_set_irq_affinity->pci_write_msi_msg->cache the msg
In kernel/irq/msi.c
msi_domain_update_chip_ops=20
        |->        if (!chip->irq_set_affinity)                            =
                                   =20
                                   chip->irq_set_affinity =3D msi_domain_se=
t_affinity

From above code, the pci/msi code should keep the caching code.

Thanks,
Peng.
>=20
> Thanks,
>=20
>         tglx