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Date: Tue, 26 Mar 2024 11:32:38 +0530
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Subject: Re: [PATCH 1/2] perf/x86/amd/core: Update stalled-cycles-* events for
 Zen 2 and later
To: Ian Rogers <irogers@google.com>, mingo@kernel.org
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
 x86@kernel.org, peterz@infradead.org, acme@kernel.org, namhyung@kernel.org,
 mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org,
 adrian.hunter@intel.com, tglx@linutronix.de, bp@alien8.de,
 eranian@google.com, ravi.bangoria@amd.com, ananth.narayan@amd.com
References: <cover.1711352180.git.sandipan.das@amd.com>
 <03d7fc8fa2a28f9be732116009025bdec1b3ec97.1711352180.git.sandipan.das@amd.com>
 <CAP-5=fVLWMnT4TV2nvbOUTTkWHYowbEOFDYqAvf1hkUEDpkKfw@mail.gmail.com>
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From: Sandipan Das <sandipan.das@amd.com>
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 =?utf-8?B?U21vRU5zZWlOUmQwdDZsYm5kaER3WEpGdEtTQkNRSHlkQnFya0orc0FhekNJ?=
 =?utf-8?B?K25BTDRyRFpLeVFFSXorY2pEL2FyWjlGTHpzbjlSdGNsNjZIOGRKanhXVFFw?=
 =?utf-8?B?MmJvV0thK0VJczh6UURySHErSUoxMmx1czZFUkRSdlJ3TVpkaFduR3FQUTd1?=
 =?utf-8?B?M3Fib3IvMGdzbEFwekhKR0lMU2xJdlRQeFRGWXZvWGhMcXlDa2ZQMWtHUC9Y?=
 =?utf-8?B?UzdEQ3c3T2FsREpjK2FpRG1MT1ovN0EvZXNuM0xPU2IzZmJqdEJHUURnMHJr?=
 =?utf-8?B?RDBCbVFOVFpOemErbUhYUmtNdnFUOG9nM3JJODJOMS9FWmVOa1ZjVHdERUl2?=
 =?utf-8?B?cmw2czFIUll6Z2Y1YzlqZ09sdU1Kb1RLMDNCOU13aWY1dS9wWDlON3NuKzlO?=
 =?utf-8?B?S2lKWXVUYmpmVDNBR2gwS0MvNURDdG11b0wwTURWa3BCSTJvdGx6OVRFM2J5?=
 =?utf-8?B?dEFTRElmSDNpV1dwbHkyL1ozbGpoanFvOTZLc1lDbXZRM2draktoWUVuV3VL?=
 =?utf-8?B?ODFPTk9OZkJRejFISS82MllBYWxuQ2NFYTJrU0RsZ1diOEdaZFhxQjJib0Fs?=
 =?utf-8?B?dTBTVXZRUmZXaGJEVjl0M1g4WWZKL0VOcWxHT2hMdnl6OXpiRDJiZk5CRWdV?=
 =?utf-8?B?Z3JVWG1oeVZWYkcvTmpzQXQ0NTRyaWsyRUZ2Z1dDbmRzSFBLWHFTWEtETCt1?=
 =?utf-8?B?aDUwNHhHZEhKR3VtRm5TT3NDN3Vwb1ZibkNRMGNsNjZPSVJ2UW9aL2w1Wm5B?=
 =?utf-8?B?Vm16ZnNxWWlzZENRSU5QcUxlUmNPM2Z1dFpFREFVOFpZZHpQc3Exd0ZYOXBS?=
 =?utf-8?B?NkhmZGxLMXkyQWdHcitZaGdNd3VuM1RKUlZ3SnRPQytWUVhuOUlIY2xZbk9y?=
 =?utf-8?B?eHQ2RWloRjgrbG1IUjRZUHpDeTZ5VHJRMisxQ3pwTEJHaEZNY1JrSmJHZnhW?=
 =?utf-8?B?YTRWaWkzVm9FSzJWaWs4VSt3Mzk1c2hkZXNUVHJsb3dFb1ZpNldnNGc3clFE?=
 =?utf-8?B?YXk5ZTJmSHVMZGdoU0F3TElMSTdnMkF2REJqdklxZW4zTFpXQThPak5CbitC?=
 =?utf-8?B?dmVUMVB0SFFkV0JDVzBTOHdCaGxJWlNKWmtEZlZZdE5ZamtjMjQxUlRZSkpy?=
 =?utf-8?B?SkVBME8rRXIrU1dxRnlVOXRlSkRTOC9GWDh0aW15OURKaFMyL0JNYkRQMkth?=
 =?utf-8?B?eGkxMm93SEw2bzJaOUIxRXhEajFTWkhXcE5HQ0FHODZWb3VNbStiMnJnQkF4?=
 =?utf-8?B?bVFtOFhvZ1diNTY5d3d2ZFVMT0pYMTNxVExMcUwyUFUvK25uNVZSSlVjRFZr?=
 =?utf-8?B?c1prWEErMWdYaHN0VWNpcEtCaVl5UDJNbllXZFhXems5MlNMMkxsQjI5V0RI?=
 =?utf-8?B?VERjQjFXUEkvbTBMb21NV0hkUHFLcUkxTzlBeDljcUlUeXNQRUZISWNwcjNa?=
 =?utf-8?B?MG9ZMER4eHR0TllGZVlqcVFPRkJmNnlxZSt1cXZTTkdTMWl4WDVHamhTOWF1?=
 =?utf-8?B?WHBYYnVQemhjSXFpZGdPOXFNdnFvQWF3c2p4WE5rZWxmTDFrek5zbGJXaVhL?=
 =?utf-8?B?Zm5jeGhMV09iU21IMFNza0x4ekRwbzdjNGtqTU1ZSFVMdzliTkEyUmJFR0U1?=
 =?utf-8?B?WUlBQ2JUZXdmMEMyZE15ZDJBOFIwMStId2hXT0pXYlAyMVh0aVlMVUQ4Sks0?=
 =?utf-8?B?UlVzQk9iclU5VkdNbm9CRExpTWNYa3liKzZPK0pCMnlZRHBIUCtCdHB2aytn?=
 =?utf-8?B?NDQyYW10ZnpWVXNmK21vRXp1N1M5endDZlJqeDdHUlpBRVl0OVRwRVg2Zk9F?=
 =?utf-8?B?OUlaTy9mSnZOUjJrQklDQVZ5QTNrRUFVbHZDS1lMR3hSRDV2V1g4dXVwc0Yy?=
 =?utf-8?Q?EvxCmCOMouABuWPVtAuAcRBvV?=
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On 3/25/2024 8:04 PM, Ian Rogers wrote:
> On Mon, Mar 25, 2024 at 12:48 AM Sandipan Das <sandipan.das@amd.com> wrote:
>>
>> AMD processors based on Zen 2 and later microarchitectures do not
>> support PMCx087 (instruction pipe stalls) which is used as the backing
>> event for "stalled-cycles-frontend" and "stalled-cycles-backend". Use
>> PMCx0A9 (cycles where micro-op queue is empty) instead to count frontend
>> stalls and remove the entry for backend stalls since there is no direct
>> replacement.
>>
>> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
> 
> This looks good to me. Should there be a Fixes tag for the sake of backports?
> 

My bad. Yes, there should a fixes tag.

Fixes: 3fe3331bb285 ("perf/x86/amd: Add event map for AMD Family 17h")

Ingo, I see that you have already pushed this to the perf/urgent branch.
Should I send a v2?

> Reviewed-by: Ian Rogers <irogers@google.com>
> 
> Thanks,
> Ian
> 
>> ---
>>  arch/x86/events/amd/core.c | 20 +++++++++++++++++---
>>  1 file changed, 17 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
>> index aec16e581f5b..afe4a809f2ed 100644
>> --- a/arch/x86/events/amd/core.c
>> +++ b/arch/x86/events/amd/core.c
>> @@ -250,7 +250,7 @@ static const u64 amd_perfmon_event_map[PERF_COUNT_HW_MAX] =
>>  /*
>>   * AMD Performance Monitor Family 17h and later:
>>   */
>> -static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> +static const u64 amd_zen1_perfmon_event_map[PERF_COUNT_HW_MAX] =
>>  {
>>         [PERF_COUNT_HW_CPU_CYCLES]              = 0x0076,
>>         [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
>> @@ -262,10 +262,24 @@ static const u64 amd_f17h_perfmon_event_map[PERF_COUNT_HW_MAX] =
>>         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = 0x0187,
>>  };
>>
>> +static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> +{
>> +       [PERF_COUNT_HW_CPU_CYCLES]              = 0x0076,
>> +       [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
>> +       [PERF_COUNT_HW_CACHE_REFERENCES]        = 0xff60,
>> +       [PERF_COUNT_HW_CACHE_MISSES]            = 0x0964,
>> +       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c2,
>> +       [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c3,
>> +       [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
>> +};
>> +
>>  static u64 amd_pmu_event_map(int hw_event)
>>  {
>> -       if (boot_cpu_data.x86 >= 0x17)
>> -               return amd_f17h_perfmon_event_map[hw_event];
>> +       if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
>> +               return amd_zen2_perfmon_event_map[hw_event];
>> +
>> +       if (cpu_feature_enabled(X86_FEATURE_ZEN1))
>> +               return amd_zen1_perfmon_event_map[hw_event];
>>
>>         return amd_perfmon_event_map[hw_event];
>>  }
>> --
>> 2.34.1
>>