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Date: Tue, 26 Mar 2024 11:46:32 +0530
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Subject: Re: [PATCH 2/2] perf/x86/amd/core: Add ref-cycles event for Zen 4 and
 later
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To: Ian Rogers <irogers@google.com>
Cc: linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
 x86@kernel.org, peterz@infradead.org, mingo@kernel.org, acme@kernel.org,
 namhyung@kernel.org, mark.rutland@arm.com,
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References: <cover.1711352180.git.sandipan.das@amd.com>
 <089155f19f7c7e65aeb1caa727a882e2ca9b8b04.1711352180.git.sandipan.das@amd.com>
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From: Sandipan Das <sandipan.das@amd.com>
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 =?utf-8?B?UXRwTjhlT01lNG5nRzVXRXgwQ3BRVTdOOXBlYXo3YnN3b3VYVEhwZE9HQ1lN?=
 =?utf-8?B?aDVQTGk1WFZPRlByTVE0cG9HUmFTU2tISk1xc1JITHRWTnpNYzNLdFlkemx5?=
 =?utf-8?B?aUszeTJjc0VDa1I4bVNqUlAwL0MzNERYYkJMc0hvcVBwU0tGMXlva3JJVWJZ?=
 =?utf-8?B?cUZvWU5ja1B2RkhXQndNQTQ0YkZkVXRXNFdsM2Rhdk5KSDljR3N3NFZYN3Ay?=
 =?utf-8?B?Ymt1aGt3T1VKKzBuRUFmWEttdHlqRmQ4Y21za3JmTjlyUlUrV2k0M0lvWEVv?=
 =?utf-8?B?Y2NIdVhhRHBVcmUyamNhcC9GOHFkYU4zNm5keGw3RmdiNzVkeUF0dEVnR3cv?=
 =?utf-8?B?QmptNWZ5enlvaXRWSTE1N0dONEFCb296SWhNcUtRRUxXRWRsdGlWd2ZBMmRi?=
 =?utf-8?B?TEhhMHBta1pLeWVnNWEyVWJYSXJlNUFvSURXQlhxSWZ3Vi9OYTE1SzNjMlcv?=
 =?utf-8?B?NTZycXM2ZlJOYmlObHdhT0pwQkp2eWpsZURaUkg1VVhsNlg5VXZUVXhnNDBi?=
 =?utf-8?B?QVlBRUQ1ZFNhdDFBVjhhcTlxeWNxOHc2SnlwYnFnZzZZM0tEd2xXWnh5RzNt?=
 =?utf-8?B?czhJV0NBYjNKR1REUGVvZjZtek5wakF0SE8vYnBVUlA3b0dGMW9yZDNWNVRD?=
 =?utf-8?B?SFZRbW9JTU53VGdiRU9uNW1oWVB3SFB1bEpNQW9sTDFITUEyVkVFc0dyYnBw?=
 =?utf-8?B?djlQa0VHQkJsV0l4TEdFQ0dYeGxmTmg2eHpqcUxEalEyVGRYWmRKdVRZbXN5?=
 =?utf-8?B?U0ZRTFl2eUo3MDRXWXlnb0ZGRS9ZTlVzNzdOQWNERmVqbHozMTA3clV0M2RC?=
 =?utf-8?B?TWdxVjR2czFzMzBTaUVGcWFTYWNDa2U1dGdsOWtmdUJJbWhCWCtHUmx4U0VS?=
 =?utf-8?B?c0E2U0ZYTE11MDB4c2dSMFNTclIwbmdLNkErSXdMM29lY21ReDdYa3dzOWh4?=
 =?utf-8?B?SVdPM3FMYk4zcFZNdUlteDFoU2tNTWROYklobGRsUVpYRkczZnpIVUI1TzZk?=
 =?utf-8?B?ck4xMkNXOW1zVVFSb0VyZitPM0p4MnNVdzVNeDMwZHl1TW1jUTdiNGpXOGpN?=
 =?utf-8?B?cnRUTmEzcnllMkFmeXFSZ1k4aHlYQzd6UUdYdExlYTIyT0dpN3M3cGYzdTQ0?=
 =?utf-8?B?RGt4WlhOblFrWUdEVzZtQmlVYTZGR3R6bmEzc2ZvaVRDeTB1L3J4bjV1NGpz?=
 =?utf-8?B?bjZwTFVkR20zbFZ6RGZzeFVHd2lkWkZpdGNFU01ERGN4U1NwQm1MV3RzNTNw?=
 =?utf-8?B?Rm9rVmg5Wk8xdU1URkhabVpGdEprcmdqZnZlZ3Q4NmsrQzJWbEx3M3c4eDhI?=
 =?utf-8?B?T0xQMHFtUEF4K25oTDB3RTNnUWpMOTFCTG5LT3hFZHNxTkJHbndzR2xGNmR5?=
 =?utf-8?B?SWo2VmpJV0RxZXNkVm5lRnFiNW04ZmdhV0QvWXZDNjg0TVhXMUdPTWFHeGRT?=
 =?utf-8?B?QlcvS1h3Q3NrTDJvOU9nWkVwN1djT2F3OFNVVjYxWkJ0NjVMdFJSdVBaMUh6?=
 =?utf-8?B?TUVnaVd1OGZyZ082S2VZelZGZEwrSHVyME1UNUhJS3F5ZVQxVEJYVDlzemtR?=
 =?utf-8?B?c0JTQUpYdHdYb0xZV3BUaUkzWVhnS0JTckxLd29ZaXdaU1ova3ovNHJRdHNT?=
 =?utf-8?B?c3hFSlpQTTg3TGk5enQ0bGVnMm9FbTFTSFhkNmdVekREZ1JiQW1HdEk1L0Nt?=
 =?utf-8?B?T3ljQWpheGE4eWRERlFtcGMzNFJ2azFXakpzVHVWZyszZmNhc2RCa0ZWemw3?=
 =?utf-8?B?SGZjT1dreGh3S3BjazF2REd4cjF2L1lpTVhFcFlVN2p6dmc3Tmlaa01YVkVk?=
 =?utf-8?B?TE5JampIUjdyQitPa3cvNld2YUxhMWxobnFRa2JyOSsyTElpVzJpUUNkL3lz?=
 =?utf-8?Q?gKo6RILVUldT07jc+sMgw7cFv?=
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On 3/25/2024 8:13 PM, Ian Rogers wrote:
> On Mon, Mar 25, 2024 at 12:48 AM Sandipan Das <sandipan.das@amd.com> wrote:
>>
>> Add the "ref-cycles" event for AMD processors based on Zen 4 and later
>> microarchitectures. The backing event is based on PMCx120 which counts
>> cycles not in halt state in P0 frequency (same as MPERF).
> 
> This reminds me that we lack smi cost and an smi_cycles metric for
> AMD, here is an Intel one:
> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json?h=perf-tools-next#n274
> The metric uses APERF but runs with freeze_on_smi set:
> https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git/tree/tools/perf/builtin-stat.c?h=perf-tools-next#n2115
> so the delta between cycles and aperf is the cycles in SMI. It would
> be great if we could get something similar on AMD.
> 

Thanks for the suggestion. I found PMCx02B ("ls_smi_rx" in perf JSONs) in
the AMD PPRs which counts the number of SMIs received but there's no way
to know how many cycles were spent in System Management Mode. I also could
not find an equivalent for the Freeze on SMI feature.

>> Signed-off-by: Sandipan Das <sandipan.das@amd.com>
> 
> Reviewed-by: Ian Rogers <irogers@google.com>
> 
> Thanks,
> Ian
> 
>> ---
>>  arch/x86/events/amd/core.c | 15 +++++++++++++++
>>  1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c
>> index afe4a809f2ed..685bfa860d67 100644
>> --- a/arch/x86/events/amd/core.c
>> +++ b/arch/x86/events/amd/core.c
>> @@ -273,8 +273,23 @@ static const u64 amd_zen2_perfmon_event_map[PERF_COUNT_HW_MAX] =
>>         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
>>  };
>>
>> +static const u64 amd_zen4_perfmon_event_map[PERF_COUNT_HW_MAX] =
>> +{
>> +       [PERF_COUNT_HW_CPU_CYCLES]              = 0x0076,
>> +       [PERF_COUNT_HW_INSTRUCTIONS]            = 0x00c0,
>> +       [PERF_COUNT_HW_CACHE_REFERENCES]        = 0xff60,
>> +       [PERF_COUNT_HW_CACHE_MISSES]            = 0x0964,
>> +       [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = 0x00c2,
>> +       [PERF_COUNT_HW_BRANCH_MISSES]           = 0x00c3,
>> +       [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00a9,
>> +       [PERF_COUNT_HW_REF_CPU_CYCLES]          = 0x100000120,
>> +};
>> +
>>  static u64 amd_pmu_event_map(int hw_event)
>>  {
>> +       if (cpu_feature_enabled(X86_FEATURE_ZEN4) || boot_cpu_data.x86 >= 0x1a)
>> +               return amd_zen4_perfmon_event_map[hw_event];
>> +
>>         if (cpu_feature_enabled(X86_FEATURE_ZEN2) || boot_cpu_data.x86 >= 0x19)
>>                 return amd_zen2_perfmon_event_map[hw_event];
>>
>> --
>> 2.34.1
>>