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Subject: Re: [PATCH v2] riscv: dts: starfive: Remove PMIC interrupt info for
 Visionfive 2 board
To: Conor Dooley <conor@kernel.org>, ganboing@gmail.com, kernel@esmil.dk,
 robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
 paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu,
 devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
 linux-kernel@vger.kernel.org, Shengyu Qu <wiagn233@outlook.com>
Cc: Conor Dooley <conor.dooley@microchip.com>, stable@vger.kernel.org
References: <TY3P286MB26116B828A34D614C09F4E8898202@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM>
 <20240326-create-motivate-2792be1692c5@spud>
From: Bo Gan <ganboing@gmail.com>
Message-ID: <f472affe-d1ef-cbdb-b5c5-76f6b3ac78b3@gmail.com>
Date: Tue, 26 Mar 2024 15:06:33 -0700
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On 3/26/24 1:37 PM, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> On Thu, 07 Mar 2024 20:21:12 +0800, Shengyu Qu wrote:
>> Interrupt line number of the AXP15060 PMIC is not a necessary part of
>> its device tree. And this would cause kernel to try to enable interrupt
>> line 0, which is not expected. So delete this part from device tree.
>>
>>
> 
> Applied to riscv-dt-fixes, thanks! And I didn't forget, so I re-wrote
> the commit message to add some more information as promised.
> 
> [1/1] riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board
>        https://git.kernel.org/conor/c/0b163f43920d
> 
> Thanks,
> Conor.
> 
Hi Conor,

Thank you very much for taking care of this. Actually the PLIC may silently
ignore the enablement of interrupt 0, so the upstream openSBI won't notice
anything. My modified version, however, will deliberately trigger a fault
for all writes to the reserved fields of PLIC, thus catching this issue.

Hope it can clarify things a bit more.

Bo