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Date: Tue, 26 Mar 2024 22:10:51 +0000
From: Conor Dooley <conor@kernel.org>
To: Bo Gan <ganboing@gmail.com>
Cc: kernel@esmil.dk, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com,
	aou@eecs.berkeley.edu, devicetree@vger.kernel.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Shengyu Qu <wiagn233@outlook.com>,
	Conor Dooley <conor.dooley@microchip.com>, stable@vger.kernel.org
Subject: Re: [PATCH v2] riscv: dts: starfive: Remove PMIC interrupt info for
 Visionfive 2 board
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On Tue, Mar 26, 2024 at 03:06:33PM -0700, Bo Gan wrote:
> On 3/26/24 1:37 PM, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >=20
> > On Thu, 07 Mar 2024 20:21:12 +0800, Shengyu Qu wrote:
> > > Interrupt line number of the AXP15060 PMIC is not a necessary part of
> > > its device tree. And this would cause kernel to try to enable interru=
pt
> > > line 0, which is not expected. So delete this part from device tree.
> > >=20
> > >=20
> >=20
> > Applied to riscv-dt-fixes, thanks! And I didn't forget, so I re-wrote
> > the commit message to add some more information as promised.
> >=20
> > [1/1] riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2=
 board
> >        https://git.kernel.org/conor/c/0b163f43920d
> >=20
> > Thanks,
> > Conor.
> >=20
> Hi Conor,
>=20
> Thank you very much for taking care of this. Actually the PLIC may silent=
ly
> ignore the enablement of interrupt 0, so the upstream openSBI won't notice
> anything. My modified version, however, will deliberately trigger a fault
> for all writes to the reserved fields of PLIC, thus catching this issue.
>=20
> Hope it can clarify things a bit more.

https://git.kernel.org/conor/c/0f74c64f0a9f

Better?


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