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Subject: Re: [PATCH v2] riscv: dts: starfive: Remove PMIC interrupt info for
 Visionfive 2 board
To: Conor Dooley <conor@kernel.org>, Bo Gan <ganboing@gmail.com>
Cc: kernel@esmil.dk, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org,
 conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com,
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 linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
 Shengyu Qu <wiagn233@outlook.com>, Conor Dooley
 <conor.dooley@microchip.com>, stable@vger.kernel.org
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From: Bo Gan <ganboing@gmail.com>
Message-ID: <222340e5-b5d7-9abc-57df-ad1478090177@gmail.com>
Date: Tue, 26 Mar 2024 15:12:13 -0700
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On 3/26/24 3:10 PM, Conor Dooley wrote:
> On Tue, Mar 26, 2024 at 03:06:33PM -0700, Bo Gan wrote:
>> On 3/26/24 1:37 PM, Conor Dooley wrote:
>>> From: Conor Dooley <conor.dooley@microchip.com>
>>>
>>> On Thu, 07 Mar 2024 20:21:12 +0800, Shengyu Qu wrote:
>>>> Interrupt line number of the AXP15060 PMIC is not a necessary part of
>>>> its device tree. And this would cause kernel to try to enable interrupt
>>>> line 0, which is not expected. So delete this part from device tree.
>>>>
>>>>
>>>
>>> Applied to riscv-dt-fixes, thanks! And I didn't forget, so I re-wrote
>>> the commit message to add some more information as promised.
>>>
>>> [1/1] riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board
>>>         https://git.kernel.org/conor/c/0b163f43920d
>>>
>>> Thanks,
>>> Conor.
>>>
>> Hi Conor,
>>
>> Thank you very much for taking care of this. Actually the PLIC may silently
>> ignore the enablement of interrupt 0, so the upstream openSBI won't notice
>> anything. My modified version, however, will deliberately trigger a fault
>> for all writes to the reserved fields of PLIC, thus catching this issue.
>>
>> Hope it can clarify things a bit more.
> 
> https://git.kernel.org/conor/c/0f74c64f0a9f
> 
> Better?
> 
Great! Thanks again.

Bo