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Wed, 27 Mar 2024 08:20:24 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 27 Mar 2024 01:20:20 -0700 From: Varadarajan Narayanan To: , , , , , , , , , , , , , CC: Varadarajan Narayanan Subject: [PATCH v4 3/3] arm64: dts: qcom: ipq9574: Add icc provider ability to gcc Date: Wed, 27 Mar 2024 13:48:50 +0530 Message-ID: <20240327081850.2924870-4-quic_varada@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240327081850.2924870-1-quic_varada@quicinc.com> References: <20240327081850.2924870-1-quic_varada@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JAnLCydGNJFcpprV6smV67DN3eHbwZKh X-Proofpoint-ORIG-GUID: JAnLCydGNJFcpprV6smV67DN3eHbwZKh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-27_04,2024-03-21_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 phishscore=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 mlxlogscore=999 bulkscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403270054 IPQ SoCs dont involve RPM in managing NoC related clocks and there is no NoC scaling. Linux itself handles these clocks. However, these should not be exposed as just clocks and align with other Qualcomm SoCs that handle these clocks from a interconnect provider. Hence include icc provider capability to the gcc node so that peripherals can use the interconnect facility to enable these clocks. Signed-off-by: Varadarajan Narayanan --- v2: Fix include file order Move to separate patch --- arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi index 7f2e5cbf3bbb..5b3e69379b1f 100644 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -306,6 +307,7 @@ gcc: clock-controller@1800000 { #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + #interconnect-cells = <1>; }; tcsr_mutex: hwlock@1905000 { -- 2.34.1