Received: by 2002:ab2:23c8:0:b0:1f2:fdbc:cb93 with SMTP id a8csp161106lqe; Wed, 27 Mar 2024 01:50:26 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCUkTLYKIj9Z+qET9ZScpoKsvP7F7cUqFgT7r3S1RWFOjmx1NQ0+/N6mjOuXPgkHinSk9n5ahJqP+VZs9ZO/6x09znvMurhbXh2kZXoAEQ== X-Google-Smtp-Source: AGHT+IGLsuBhyHaHd0ewHv1utVOwoF+HuHu9C+VJGaUc9CpbHXmUPGM2Nxstkp+j4EV2xKCp3fGe X-Received: by 2002:a17:902:7007:b0:1e0:9e32:e3dd with SMTP id y7-20020a170902700700b001e09e32e3ddmr612792plk.61.1711529426600; Wed, 27 Mar 2024 01:50:26 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1711529426; cv=pass; d=google.com; s=arc-20160816; b=bfYT1QpeZD48y4AueEKMpwUm6SdRs+/QBOdlh65BwdyX81VMJ7syL3oRrk0RmjvSKL v69M4bsdwH5Wv5RHz8SQR9XF7ng8lzJs1DzFO3Tm9mEYLx4KffDbPwKAzJ5ve7n2c+H6 joellEk0gOVSBykw4E6BdNXHuaO3sqT8lFVp4WP5nlLkFvLE1xE7C1mkTz5ud/KpJXFq mP7ewciPHYmlIXTuUqOs+tBHSwVJLMBymQlz+N5iZNgw6Tq65fkuZPABGfU9etLEeLmO gBaTXpJCf+Ljpt4hnhQl1XmeEV90n+WWA6DmO5dkIQkleQ8eUAiaqBqnhYl9Iuh4L+vD 0dzg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :dkim-signature; bh=pLYlN16RyWsxEwBzjLz8ThQC9SQHV7u2gPr9C5zHFq8=; fh=dKJNxK/8AgTL/SF0S/p+aN6QKLf/0Q+d84VkMLuyJTY=; b=C+9UF6+dvg52SVfX3eL3h8QctMxFzgGVeTbAQImJKGAv6vVrevgmRSgLZhb1hbMOaM ERaeK/CfFTbJW9AwiLdTn5gYK5wdA1TmBv0l8qeHs3Xj52O4IxgDbhdpi6wqgGooK0By AnHkj9p3K4y+0Pw08RR5KNquhHrZPi6+8QFtqiP2MjUx12b8B45/fWtg/ZvyY/m79X0S 98t5vh6VEoQwagGAN3fnFl9NxF0IsVxgaq9yzpyE7ygyCcfa7BMltD6xz9OIP1rirlcA 8RO050jxDCWjXbAnkOytWNn2dm1fRS/IPP/tzFJBj503SZAjBsp50Y84vAUjuIAIGmkW 5ycg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rq5zoPr2; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-120569-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-120569-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id u10-20020a17090341ca00b001e0b86254e1si6480394ple.307.2024.03.27.01.50.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:50:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-120569-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rq5zoPr2; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-120569-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-120569-linux.lists.archive=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 3F5622987CD for ; Wed, 27 Mar 2024 08:50:26 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E8B08374E9; Wed, 27 Mar 2024 08:50:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Rq5zoPr2" Received: from mail-yb1-f172.google.com (mail-yb1-f172.google.com [209.85.219.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17F882C1A0 for ; Wed, 27 Mar 2024 08:50:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711529410; cv=none; b=JRSBV0LtY1jpYTpLO8Ip//kIpWhMcjNvhT97Ynm2AUunhC55+aHv+VUiEzUNqxPqSBFyXRsMr6A6fPcvjFflDbLH3ehhY4Wr8g7Z1l2ddduoDEsOT7hB7S6FNUqYZfFMUBO9SH3E15ud0Bo8cs7sZE3rhO/aTC+epzn5ZhooTAY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711529410; c=relaxed/simple; bh=G1T8j6kmbh5YKnwus41DkuQV/P9KjTNsZ6i0EFzmw3U=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=gi/aIZkCg6pzh8uE6kIAVaL+wLN5mjj64pIJIS6nKjz2cT0FdrwnfCU40Mq7PetyKpA94ihYJFhCo3rnFVTdmSsbUV0JXZF09FOAlQ1KGgYYXGG01ICDdo/4IynKYKq+teX3Y5uJmH2PeQzYciVwSfNv7UfzSIyTor8151ZEjVM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Rq5zoPr2; arc=none smtp.client-ip=209.85.219.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Received: by mail-yb1-f172.google.com with SMTP id 3f1490d57ef6-db3a09e96daso6048635276.3 for ; Wed, 27 Mar 2024 01:50:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1711529407; x=1712134207; darn=vger.kernel.org; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=pLYlN16RyWsxEwBzjLz8ThQC9SQHV7u2gPr9C5zHFq8=; b=Rq5zoPr2vFNS3kDEmj8NfosnY1yFn+nDuLgPdtu3u8ogbcqnfAT4xNf5v8J35D53QF E1S+NKtzbm0ovV34T9i/NJvNg+3zhxNeSD1D5jGci6ltHW0rcmhqs8qzUtCl5f2rgL8b f9VblLDCChd1kM1RPXHmBLc8zcPnqQENBUG9c4yRuNW9AgjMW30uoFFQHNwDOpr1bFnb z3WnK9WheVbFJcciKmqFkUqTVeG/PWmxXqADYzo/FLLV4QJuqppFn8sR80dPcn3zqgei MoBO2VRCz4xuhB6k2Elgajc/TZS8fjzQEADpysiuug6vyZdcVbIIuK78ARo2duZGsDDy bKRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711529407; x=1712134207; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=pLYlN16RyWsxEwBzjLz8ThQC9SQHV7u2gPr9C5zHFq8=; b=e5+kDrE5NLyM8TV9NBw0/ALmTlzpvlXyKf3dPi9oosVolfmRtdQ+SIyTAHl/X0hgbo 0jmVN/vTqWcH8iIWh83wZBt8I/S0kvjYrkopc8KyiOFLfJcpPzXnRrx6hJcpvbO1G0ZG FJCAsmh+AvOmp/x7mFvPWs5oLvLWIbFIuJ/Ej0q197XujMf7+Y2aGL4WoteujAHT2i+G kMzXGxj+vfJsXBKVkl71cdG/HtqdzSKXONajDQ7J5jndojjZeGX0+NjMgmnRzMg0PAOT 0wEoKRQQrRmk6UPCW8qdPAR8fBCjeOxkN/9on7tYSjeD1nsRMnk6BYKvPFWi9EqgK6Jp /E4A== X-Forwarded-Encrypted: i=1; AJvYcCXrrW0KSMWAGTZF1hHiiJYeyFUu5bMcTGuuQVVVlSKdeiHkZoakBzO7TmoQVI99KOo2mc01wfzd/HYSHc4vxZ9IRgRx+IdD+AW6j0C3 X-Gm-Message-State: AOJu0Ywq9zEJ4FLQDdDbBZ8igO5TIP4m4Sm+vpUDIHKpMd32Ox/RmSls AaIu/wvbrSqV2cvtSHPKXDPLuQ9KFGibr73bxaNDBGDvpHmN0xQ8b0QpmUrVysMdveaIs8BS3em RCYLXMvIbg1s249OJHE6uW10qDtFHbKCSFwrHPw== X-Received: by 2002:a25:aa4b:0:b0:dc7:3166:ad25 with SMTP id s69-20020a25aa4b000000b00dc73166ad25mr414150ybi.25.1711529407085; Wed, 27 Mar 2024 01:50:07 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240327081850.2924870-1-quic_varada@quicinc.com> <20240327081850.2924870-3-quic_varada@quicinc.com> In-Reply-To: <20240327081850.2924870-3-quic_varada@quicinc.com> From: Dmitry Baryshkov Date: Wed, 27 Mar 2024 10:49:56 +0200 Message-ID: Subject: Re: [PATCH v4 2/3] clk: qcom: add IPQ9574 interconnect clocks support To: Varadarajan Narayanan Cc: andersson@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, djakov@kernel.org, quic_anusha@quicinc.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Content-Type: text/plain; charset="UTF-8" On Wed, 27 Mar 2024 at 10:21, Varadarajan Narayanan wrote: > > Unlike MSM platforms that manage NoC related clocks and scaling > from RPM, IPQ SoCs dont involve RPM in managing NoC related > clocks and there is no NoC scaling. > > However, there is a requirement to enable some NoC interface > clocks for accessing the peripheral controllers present on > these NoCs. Though exposing these as normal clocks would work, > having a minimalistic interconnect driver to handle these clocks > would make it consistent with other Qualcomm platforms resulting > in common code paths. This is similar to msm8996-cbf's usage of > icc-clk framework. > > Signed-off-by: Varadarajan Narayanan > --- > v4: Use clk_hw instead of indices > Do icc register in qcom_cc_probe() call stream > Add icc clock info to qcom_cc_desc structure > v3: Use indexed identifiers here to avoid confusion > Fix error messages and move to common.c > v2: Move DTS to separate patch > Update commit log > Auto select CONFIG_INTERCONNECT & CONFIG_INTERCONNECT_CLK to fix build error > --- > drivers/clk/qcom/Kconfig | 2 ++ > drivers/clk/qcom/common.c | 34 ++++++++++++++++++++- > drivers/clk/qcom/common.h | 4 ++- > drivers/clk/qcom/gcc-ipq9574.c | 54 ++++++++++++++++++++++++++++++++++ These changes must be separate. > 4 files changed, 92 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index 8ab08e7b5b6c..af73a0b396eb 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -243,6 +243,8 @@ config IPQ_GCC_8074 > > config IPQ_GCC_9574 > tristate "IPQ9574 Global Clock Controller" > + select INTERCONNECT > + select INTERCONNECT_CLK > help > Support for global clock controller on ipq9574 devices. > Say Y if you want to use peripheral devices such as UART, SPI, > diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c > index 75f09e6e057e..523d30d0ccbc 100644 > --- a/drivers/clk/qcom/common.c > +++ b/drivers/clk/qcom/common.c > @@ -8,6 +8,8 @@ > #include > #include > #include > +#include > +#include > #include > #include > > @@ -234,6 +236,36 @@ static struct clk_hw *qcom_cc_clk_hw_get(struct of_phandle_args *clkspec, > return cc->rclks[idx] ? &cc->rclks[idx]->hw : NULL; > } > > +static int qcom_cc_icc_register(struct device *dev, > + const struct qcom_cc_desc *desc) > +{ > +#if IS_ENABLED(CONFIG_INTERCONNECT_CLK) General recommendation is to avoid #ifs inside function code. Please move them outside and add an empty stub. > + struct icc_provider *provider; > + struct icc_clk_data *icd; > + int i; > + > + if (!desc->icc_hws) > + return 0; > + > + icd = devm_kcalloc(dev, desc->num_icc_hws, sizeof(*icd), GFP_KERNEL); > + if (!icd) > + return dev_err_probe(dev, -ENOMEM, "malloc for icc clock data failed\n"); No need to. > + > + for (i = 0; i < desc->num_icc_hws; i++) { > + icd[i].clk = devm_clk_hw_get_clk(dev, desc->icc_hws[i], ""); Passing an empty string is not correct from the CCF point of view. > + if (IS_ERR_OR_NULL(icd[i].clk)) > + return dev_err_probe(dev, -ENOENT, "icc clock not found\n"); No, just IS_ERR and PTR_ERR. Don't throw away the resulting code. In most of the case IS_ERR_OR_NULL is not correct. The function either returns NULL or returns an error pointer. It can not be both. > + icd[i].name = clk_hw_get_name(desc->icc_hws[i]); > + } > + > + provider = icc_clk_register(dev, desc->first_id, desc->num_icc_hws, icd); > + if (IS_ERR_OR_NULL(provider)) just use PTR_ERR_OR_ZERO Also note that there is no qcom_cc_remove, so please add devm_icc_clk_register() and use it here: return PTR_ERR_OR_ZERO(devm_icc_clk_register(dev, ...)); > + return dev_err_probe(dev, PTR_ERR(provider), > + "icc_clk_register failed\n"); > +#endif > + return 0; > +} > + > int qcom_cc_really_probe(struct platform_device *pdev, > const struct qcom_cc_desc *desc, struct regmap *regmap) > { > @@ -303,7 +335,7 @@ int qcom_cc_really_probe(struct platform_device *pdev, > if (ret) > return ret; > > - return 0; > + return qcom_cc_icc_register(dev, desc); > } > EXPORT_SYMBOL_GPL(qcom_cc_really_probe); > > diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h > index 9c8f7b798d9f..3c3a07f6dcb9 100644 > --- a/drivers/clk/qcom/common.h > +++ b/drivers/clk/qcom/common.h > @@ -29,6 +29,9 @@ struct qcom_cc_desc { > size_t num_gdscs; > struct clk_hw **clk_hws; > size_t num_clk_hws; > + struct clk_hw **icc_hws; > + size_t num_icc_hws; > + unsigned int first_id; > }; > > /** > @@ -65,5 +68,4 @@ extern int qcom_cc_probe(struct platform_device *pdev, > const struct qcom_cc_desc *desc); > extern int qcom_cc_probe_by_index(struct platform_device *pdev, int index, > const struct qcom_cc_desc *desc); > - > #endif > diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c > index 0a3f846695b8..187fd9dcdf49 100644 > --- a/drivers/clk/qcom/gcc-ipq9574.c > +++ b/drivers/clk/qcom/gcc-ipq9574.c > @@ -12,6 +12,7 @@ > > #include > #include > +#include > > #include "clk-alpha-pll.h" > #include "clk-branch.h" > @@ -4301,6 +4302,56 @@ static const struct qcom_reset_map gcc_ipq9574_resets[] = { > [GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 }, > }; > > +#define IPQ_APPS_ID 9574 /* some unique value */ > + > +enum { > + ICC_ANOC_PCIE0, > + ICC_SNOC_PCIE0, > + ICC_ANOC_PCIE1, > + ICC_SNOC_PCIE1, > + ICC_ANOC_PCIE2, > + ICC_SNOC_PCIE2, > + ICC_ANOC_PCIE3, > + ICC_SNOC_PCIE3, > + ICC_SNOC_USB, > + ICC_ANOC_USB_AXI, > + ICC_NSSNOC_NSSCC, > + ICC_NSSNOC_SNOC_0, > + ICC_NSSNOC_SNOC_1, > + ICC_NSSNOC_PCNOC_1, > + ICC_NSSNOC_QOSGEN_REF, > + ICC_NSSNOC_TIMEOUT_REF, > + ICC_NSSNOC_XO_DCD, > + ICC_NSSNOC_ATB, > + ICC_MEM_NOC_NSSNOC, > + ICC_NSSNOC_MEMNOC, > + ICC_NSSNOC_MEM_NOC_1, > +}; > + > +static struct clk_hw *icc_ipq9574_hws[] = { > + [ICC_ANOC_PCIE0] = &gcc_anoc_pcie0_1lane_m_clk.clkr.hw, > + [ICC_SNOC_PCIE0] = &gcc_anoc_pcie1_1lane_m_clk.clkr.hw, > + [ICC_ANOC_PCIE1] = &gcc_anoc_pcie2_2lane_m_clk.clkr.hw, > + [ICC_SNOC_PCIE1] = &gcc_anoc_pcie3_2lane_m_clk.clkr.hw, > + [ICC_ANOC_PCIE2] = &gcc_snoc_pcie0_1lane_s_clk.clkr.hw, > + [ICC_SNOC_PCIE2] = &gcc_snoc_pcie1_1lane_s_clk.clkr.hw, > + [ICC_ANOC_PCIE3] = &gcc_snoc_pcie2_2lane_s_clk.clkr.hw, > + [ICC_SNOC_PCIE3] = &gcc_snoc_pcie3_2lane_s_clk.clkr.hw, > + [ICC_SNOC_USB] = &gcc_snoc_usb_clk.clkr.hw, > + [ICC_ANOC_USB_AXI] = &gcc_anoc_usb_axi_clk.clkr.hw, > + [ICC_NSSNOC_NSSCC] = &gcc_nssnoc_nsscc_clk.clkr.hw, > + [ICC_NSSNOC_SNOC_0] = &gcc_nssnoc_snoc_clk.clkr.hw, > + [ICC_NSSNOC_SNOC_1] = &gcc_nssnoc_snoc_1_clk.clkr.hw, > + [ICC_NSSNOC_PCNOC_1] = &gcc_nssnoc_pcnoc_1_clk.clkr.hw, > + [ICC_NSSNOC_QOSGEN_REF] = &gcc_nssnoc_qosgen_ref_clk.clkr.hw, > + [ICC_NSSNOC_TIMEOUT_REF] = &gcc_nssnoc_timeout_ref_clk.clkr.hw, > + [ICC_NSSNOC_XO_DCD] = &gcc_nssnoc_xo_dcd_clk.clkr.hw, > + [ICC_NSSNOC_ATB] = &gcc_nssnoc_atb_clk.clkr.hw, > + [ICC_MEM_NOC_NSSNOC] = &gcc_mem_noc_nssnoc_clk.clkr.hw, > + [ICC_NSSNOC_MEMNOC] = &gcc_nssnoc_memnoc_clk.clkr.hw, > + [ICC_NSSNOC_MEM_NOC_1] = &gcc_nssnoc_mem_noc_1_clk.clkr.hw, > +}; > + > static const struct of_device_id gcc_ipq9574_match_table[] = { > { .compatible = "qcom,ipq9574-gcc" }, > { } > @@ -4323,6 +4374,9 @@ static const struct qcom_cc_desc gcc_ipq9574_desc = { > .num_resets = ARRAY_SIZE(gcc_ipq9574_resets), > .clk_hws = gcc_ipq9574_hws, > .num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws), > + .icc_hws = icc_ipq9574_hws, > + .num_icc_hws = ARRAY_SIZE(icc_ipq9574_hws), > + .first_id = IPQ_APPS_ID, > }; > > static int gcc_ipq9574_probe(struct platform_device *pdev) > -- > 2.34.1 > > -- With best wishes Dmitry