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[2001:b400:e383:3566:13c:5a87:9abc:381e]) by smtp.gmail.com with ESMTPSA id h12-20020a170902eecc00b001e0501d3058sm8356848plb.63.2024.03.27.01.53.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 01:53:40 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 1/4] ARM: dts: aspeed: Add the AST2500 WDT with SCU register Date: Wed, 27 Mar 2024 16:53:27 +0800 Message-Id: <20240327085330.3281697-2-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> References: <20240327085330.3281697-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The AST2500 WDT references the System Control Unit register for its operation. Signed-off-by: Peter Yin --- arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index 04f98d1dbb97..5fd12c057c31 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -410,12 +410,14 @@ wdt1: watchdog@1e785000 { compatible = "aspeed,ast2500-wdt"; reg = <0x1e785000 0x20>; clocks = <&syscon ASPEED_CLK_APB>; + aspeed,scu = <&syscon>; }; wdt2: watchdog@1e785020 { compatible = "aspeed,ast2500-wdt"; reg = <0x1e785020 0x20>; clocks = <&syscon ASPEED_CLK_APB>; + aspeed,scu = <&syscon>; }; wdt3: watchdog@1e785040 { @@ -423,6 +425,7 @@ wdt3: watchdog@1e785040 { reg = <0x1e785040 0x20>; clocks = <&syscon ASPEED_CLK_APB>; status = "disabled"; + aspeed,scu = <&syscon>; }; pwm_tacho: pwm-tacho-controller@1e786000 { -- 2.25.1