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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF000015CC.mail.protection.outlook.com (10.167.241.202) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7409.10 via Frontend Transport; Wed, 27 Mar 2024 18:52:44 +0000 Received: from jallen-jump-host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Wed, 27 Mar 2024 13:52:44 -0500 From: John Allen To: , , , CC: , , , John Allen Subject: [PATCH v2 2/4] RAS/AMD/ATL: Expand helpers for adding and removing base and hole Date: Wed, 27 Mar 2024 18:52:20 +0000 Message-ID: <20240327185222.98998-3-john.allen@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240327185222.98998-1-john.allen@amd.com> References: <20240327185222.98998-1-john.allen@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CC:EE_|DS7PR12MB8419:EE_ X-MS-Office365-Filtering-Correlation-Id: acc80b91-7c9c-4b6d-d467-08dc4e8f16c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Mar 2024 18:52:44.8078 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: acc80b91-7c9c-4b6d-d467-08dc4e8f16c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8419 The existing helpers for adding and removing the base and legacy MMIO hole operate on the ret_addr stored in the addr_ctx struct. This works for the existing use case as adding and removing the base and hole is only done once for an address that is already stored in ret_addr as part of translation. However, in the Data Fabric 4.5 non-power-of-2 cases, we will add and remove the base and hole temporarily to check for correctness on addresses other than ret_addr multiple times throughout translation. Modify the helpers to take any address as a parameter and return the resulting address after adding or removing the hole. This will allow for more simply adding and removing the base and hole from any address without having to store them in the ret_addr field of the addr_ctx struct. Signed-off-by: John Allen --- v2: - Make remove_base_and_hole the inverse of add_base_and_hole, removing the hole first and then removing the base. - Improve commit description. --- drivers/ras/amd/atl/core.c | 43 ++++++++++++++++++++++------------ drivers/ras/amd/atl/internal.h | 3 +++ 2 files changed, 31 insertions(+), 15 deletions(-) diff --git a/drivers/ras/amd/atl/core.c b/drivers/ras/amd/atl/core.c index 63513d972c07..d45f9948c0ab 100644 --- a/drivers/ras/amd/atl/core.c +++ b/drivers/ras/amd/atl/core.c @@ -49,15 +49,26 @@ static bool legacy_hole_en(struct addr_ctx *ctx) return FIELD_GET(DF_LEGACY_MMIO_HOLE_EN, reg); } -static int add_legacy_hole(struct addr_ctx *ctx) +static u64 add_legacy_hole(struct addr_ctx *ctx, u64 addr) { if (!legacy_hole_en(ctx)) - return 0; + return addr; - if (ctx->ret_addr >= df_cfg.dram_hole_base) - ctx->ret_addr += (BIT_ULL(32) - df_cfg.dram_hole_base); + if (addr >= df_cfg.dram_hole_base) + addr += (BIT_ULL(32) - df_cfg.dram_hole_base); - return 0; + return addr; +} + +static u64 remove_legacy_hole(struct addr_ctx *ctx, u64 addr) +{ + if (!legacy_hole_en(ctx)) + return addr; + + if (addr >= df_cfg.dram_hole_base) + addr -= (BIT_ULL(32) - df_cfg.dram_hole_base); + + return addr; } static u64 get_base_addr(struct addr_ctx *ctx) @@ -72,14 +83,16 @@ static u64 get_base_addr(struct addr_ctx *ctx) return base_addr << DF_DRAM_BASE_LIMIT_LSB; } -static int add_base_and_hole(struct addr_ctx *ctx) +u64 add_base_and_hole(struct addr_ctx *ctx, u64 addr) { - ctx->ret_addr += get_base_addr(ctx); - - if (add_legacy_hole(ctx)) - return -EINVAL; + addr += get_base_addr(ctx); + return add_legacy_hole(ctx, addr); +} - return 0; +u64 remove_base_and_hole(struct addr_ctx *ctx, u64 addr) +{ + remove_legacy_hole(ctx, addr); + return addr - get_base_addr(ctx); } static bool late_hole_remove(struct addr_ctx *ctx) @@ -123,14 +136,14 @@ unsigned long norm_to_sys_addr(u8 socket_id, u8 die_id, u8 coh_st_inst_id, unsig if (denormalize_address(&ctx)) return -EINVAL; - if (!late_hole_remove(&ctx) && add_base_and_hole(&ctx)) - return -EINVAL; + if (!late_hole_remove(&ctx)) + ctx.ret_addr = add_base_and_hole(&ctx, ctx.ret_addr); if (dehash_address(&ctx)) return -EINVAL; - if (late_hole_remove(&ctx) && add_base_and_hole(&ctx)) - return -EINVAL; + if (late_hole_remove(&ctx)) + ctx.ret_addr = add_base_and_hole(&ctx, ctx.ret_addr); if (addr_over_limit(&ctx)) return -EINVAL; diff --git a/drivers/ras/amd/atl/internal.h b/drivers/ras/amd/atl/internal.h index 1413c8ddc6c5..05b870fcb24e 100644 --- a/drivers/ras/amd/atl/internal.h +++ b/drivers/ras/amd/atl/internal.h @@ -236,6 +236,9 @@ int dehash_address(struct addr_ctx *ctx); unsigned long norm_to_sys_addr(u8 socket_id, u8 die_id, u8 coh_st_inst_id, unsigned long addr); unsigned long convert_umc_mca_addr_to_sys_addr(struct atl_err *err); +u64 add_base_and_hole(struct addr_ctx *ctx, u64 addr); +u64 remove_base_and_hole(struct addr_ctx *ctx, u64 addr); + /* * Make a gap in @data that is @num_bits long starting at @bit_num. * e.g. data = 11111111'b -- 2.34.1