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From: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
CC: Caleb Connolly <caleb.connolly@linaro.org>,
        Volodymyr Babchuk
	<Volodymyr_Babchuk@epam.com>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad
 Dybcio <konrad.dybcio@linaro.org>,
        "linux-arm-msm@vger.kernel.org"
	<linux-arm-msm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>
Subject: [PATCH] soc: qcom: cmd-db: map shared memory as WT, not WB
Thread-Topic: [PATCH] soc: qcom: cmd-db: map shared memory as WT, not WB
Thread-Index: AQHagIKviCrPH112HEOpsjr5BCtYWA==
Date: Wed, 27 Mar 2024 20:09:34 +0000
Message-ID: <20240327200917.2576034-1-volodymyr_babchuk@epam.com>
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It appears that hardware does not like cacheable accesses to this
region. Trying to access this shared memory region as Normal Memory
leads to secure interrupt which causes an endless loop somewhere in
Trust Zone.

The only reason it is working right now is because Qualcomm Hypervisor
maps the same region as Non-Cacheable memory in Stage 2 translation
tables. The issue manifests if we want to use another hypervisor (like
Xen or KVM), which does not know anything about those specific
mappings. This patch fixes the issue by mapping the shared memory as
Write-Through. This removes dependency on correct mappings in Stage 2
tables.

I tested this on SA8155P with Xen.

Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
---
 drivers/soc/qcom/cmd-db.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c
index a5fd68411bed5..dd5ababdb476c 100644
--- a/drivers/soc/qcom/cmd-db.c
+++ b/drivers/soc/qcom/cmd-db.c
@@ -324,7 +324,7 @@ static int cmd_db_dev_probe(struct platform_device *pde=
v)
 		return -EINVAL;
 	}
=20
-	cmd_db_header =3D memremap(rmem->base, rmem->size, MEMREMAP_WB);
+	cmd_db_header =3D memremap(rmem->base, rmem->size, MEMREMAP_WT);
 	if (!cmd_db_header) {
 		ret =3D -ENOMEM;
 		cmd_db_header =3D NULL;
--=20
2.43.0