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References: <20240327214831.1544595-1-helgaas@kernel.org> <20240327214831.1544595-3-helgaas@kernel.org>
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From: Ben Chuang <benchuanggli@gmail.com>
Date: Thu, 28 Mar 2024 09:01:39 +0800
Message-ID: <CACT4zj9BFwMLsDSzNQ=wHSBCHqoydggtM-7-7rsfo0pRV2iLEg@mail.gmail.com>
Subject: Re: [PATCH 2/2] mmc: sdhci-pci-gli: Use pci_set_power_state(), not
 direct PMCSR writes
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Adrian Hunter <adrian.hunter@intel.com>, Ulf Hansson <ulf.hansson@linaro.org>, 
	Victor Shih <victor.shih@genesyslogic.com.tw>, 
	Ben Chuang <ben.chuang@genesyslogic.com.tw>, 
	Kai-Heng Feng <kai.heng.geng@canonical.com>, Sven van Ashbrook <svenva@chromium.org>, 
	Stanislaw Kardach <skardach@google.com>, Brian Norris <briannorris@chromium.org>, 
	Jason Lai <jasonlai.genesyslogic@gmail.com>, Renius Chen <reniuschengl@gmail.com>, 
	linux-pci@vger.kernel.org, linux-mmc@vger.kernel.org, 
	linux-kernel@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>
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On Thu, Mar 28, 2024 at 5:49=E2=80=AFAM Bjorn Helgaas <helgaas@kernel.org> =
wrote:
>
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> d7133797e9e1 ("mmc: sdhci-pci-gli: A workaround to allow GL9750 to enter
> ASPM L1.2") and 36ed2fd32b2c ("mmc: sdhci-pci-gli: A workaround to allow
> GL9755 to enter ASPM L1.2") added writes to the Control register in the
> Power Management Capability to put the device in D3hot and back to D0.
>
> Use the pci_set_power_state() interface instead because these are generic
> operations that don't need to be driver-specific.  Also, the PCI spec
> requires some delays after these power transitions, and
> pci_set_power_state() takes care of those, while d7133797e9e1 and
> 36ed2fd32b2c did not.
>
> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Hi Bjorn,

Thanks. It looks better than the vendor specific.

Best regards,
Ben Chuang

> ---
>  drivers/mmc/host/sdhci-pci-gli.c | 20 ++++----------------
>  1 file changed, 4 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pc=
i-gli.c
> index 3d5543581537..0f81586a19df 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -25,9 +25,6 @@
>  #define   GLI_9750_WT_EN_ON        0x1
>  #define   GLI_9750_WT_EN_OFF       0x0
>
> -#define PCI_GLI_9750_PM_CTRL   0xFC
> -#define   PCI_GLI_9750_PM_STATE          GENMASK(1, 0)
> -
>  #define SDHCI_GLI_9750_CFG2          0x848
>  #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
>  #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
> @@ -149,9 +146,6 @@
>  #define PCI_GLI_9755_MISC          0x78
>  #define   PCI_GLI_9755_MISC_SSC_OFF    BIT(26)
>
> -#define PCI_GLI_9755_PM_CTRL     0xFC
> -#define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
> -
>  #define SDHCI_GLI_9767_GM_BURST_SIZE                   0x510
>  #define   SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET    BIT(8)
>
> @@ -556,11 +550,8 @@ static void gl9750_hw_setting(struct sdhci_host *hos=
t)
>         sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
>
>         /* toggle PM state to allow GL9750 to enter ASPM L1.2 */
> -       pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value);
> -       value |=3D PCI_GLI_9750_PM_STATE;
> -       pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
> -       value &=3D ~PCI_GLI_9750_PM_STATE;
> -       pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
> +       pci_set_power_state(pdev, PCI_D3hot);
> +       pci_set_power_state(pdev, PCI_D0);
>
>         /* mask the replay timer timeout of AER */
>         aer =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
> @@ -774,11 +765,8 @@ static void gl9755_hw_setting(struct sdhci_pci_slot =
*slot)
>         pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
>
>         /* toggle PM state to allow GL9755 to enter ASPM L1.2 */
> -       pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
> -       value |=3D PCI_GLI_9755_PM_STATE;
> -       pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> -       value &=3D ~PCI_GLI_9755_PM_STATE;
> -       pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
> +       pci_set_power_state(pdev, PCI_D3hot);
> +       pci_set_power_state(pdev, PCI_D0);
>
>         /* mask the replay timer timeout of AER */
>         aer =3D pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
> --
> 2.34.1
>
>