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[2001:b400:e355:7eb0:17c6:c47d:d4ee:f9e8]) by smtp.gmail.com with ESMTPSA id d25-20020aa78699000000b006ea858ea901sm229256pfo.210.2024.03.27.19.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Mar 2024 19:22:52 -0700 (PDT) From: Peter Yin To: patrick@stwcx.xyz, Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus Date: Thu, 28 Mar 2024 10:22:31 +0800 Message-Id: <20240328022231.3649741-5-peteryin.openbmc@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240328022231.3649741-1-peteryin.openbmc@gmail.com> References: <20240328022231.3649741-1-peteryin.openbmc@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600 Regarding the AST2600 specification, the WDTn Timeout Status Register (WDT10) has bit 1 reserved. Bit 1 of the status register indicates on ast2500 if the boot was from the second boot source. It does not indicate that the most recent reset was triggered by the watchdog. The code should just be changed to set WDIOF_CARDRESET if bit 0 of the status register is set. Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or ast2500 SCU3C when bit1 is set. Signed-off-by: Peter Yin --- drivers/watchdog/aspeed_wdt.c | 35 +++++++++++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c index b4773a6aaf8c..0e7ef860cbdc 100644 --- a/drivers/watchdog/aspeed_wdt.c +++ b/drivers/watchdog/aspeed_wdt.c @@ -11,10 +11,12 @@ #include #include #include +#include #include #include #include #include +#include #include static bool nowayout = WATCHDOG_NOWAYOUT; @@ -77,11 +79,19 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table); #define WDT_TIMEOUT_STATUS 0x10 #define WDT_TIMEOUT_STATUS_IRQ BIT(2) #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1) +#define WDT_TIMEOUT_STATUS_EVENT BIT(0) #define WDT_CLEAR_TIMEOUT_STATUS 0x14 #define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0) #define WDT_RESET_MASK1 0x1c #define WDT_RESET_MASK2 0x20 +/* + * Ast2600 SCU74 bit1 is External reset flag + * Ast2500 SCU3C bit1 is External reset flag + */ +#define AST2500_SYSTEM_RESET_EVENT 0x3C +#define AST2600_SYSTEM_RESET_EVENT 0x74 +#define EXTERN_RESET_FLAG BIT(1) /* * WDT_RESET_WIDTH controls the characteristics of the external pulse (if * enabled), specifically: @@ -330,6 +340,11 @@ static int aspeed_wdt_probe(struct platform_device *pdev) if (IS_ERR(wdt->base)) return PTR_ERR(wdt->base); + struct regmap *scu_base = syscon_regmap_lookup_by_phandle(dev->of_node, + "aspeed,scu"); + if (IS_ERR(scu_base)) + return PTR_ERR(scu_base); + wdt->wdd.info = &aspeed_wdt_info; if (wdt->cfg->irq_mask) { @@ -459,14 +474,26 @@ static int aspeed_wdt_probe(struct platform_device *pdev) } status = readl(wdt->base + WDT_TIMEOUT_STATUS); - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) { + if (status & WDT_TIMEOUT_STATUS_EVENT) wdt->wdd.bootstatus = WDIOF_CARDRESET; - if (of_device_is_compatible(np, "aspeed,ast2400-wdt") || - of_device_is_compatible(np, "aspeed,ast2500-wdt")) - wdt->wdd.groups = bswitch_groups; + if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) { + ret = regmap_read(scu_base, + AST2600_SYSTEM_RESET_EVENT, + &status); + } else { + ret = regmap_read(scu_base, + AST2500_SYSTEM_RESET_EVENT, + &status); + wdt->wdd.groups = bswitch_groups; } + /* + * Reset cause by Extern Reset + */ + if (status & EXTERN_RESET_FLAG && !ret) + wdt->wdd.bootstatus |= WDIOF_EXTERN1; + dev_set_drvdata(dev, wdt); return devm_watchdog_register_device(dev, &wdt->wdd); -- 2.25.1