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Thu, 28 Mar 2024 06:52:39 GMT Received: from [10.253.14.163] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Wed, 27 Mar 2024 23:52:36 -0700 Message-ID: <98c668b6-7595-2c0a-ebe5-2f729d29b618@quicinc.com> Date: Thu, 28 Mar 2024 14:52:32 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [RESEND PATCH v6 3/3] input: pm8xxx-vibrator: add new SPMI vibrator support Content-Language: en-US To: Dmitry Torokhov CC: Dmitry Baryshkov , , , , , , , Konrad Dybcio , , , , , , Luca Weiss References: <20230922083801.3056724-1-quic_fenglinw@quicinc.com> <20230922083801.3056724-4-quic_fenglinw@quicinc.com> <12887370-0ada-359b-8a4f-18a28495c69a@quicinc.com> From: Fenglin Wu In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ma9H1W9QcbP1vqR2emR-ZoEwdYE7ALfs X-Proofpoint-GUID: ma9H1W9QcbP1vqR2emR-ZoEwdYE7ALfs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-28_05,2024-03-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 priorityscore=1501 phishscore=0 malwarescore=0 mlxscore=0 mlxlogscore=999 suspectscore=0 clxscore=1011 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403210001 definitions=main-2403280042 On 2023/10/1 0:17, Dmitry Torokhov wrote: > On Mon, Sep 25, 2023 at 10:54:45AM +0800, Fenglin Wu wrote: >> >> >> On 9/24/2023 3:07 AM, Dmitry Baryshkov wrote: >>>> + >>>> + switch (vib->data->hw_type) { >>>> + case SSBI_VIB: >>>> mask = SSBI_VIB_DRV_LEVEL_MASK; >>>> shift = SSBI_VIB_DRV_SHIFT; >>>> + break; >>>> + case SPMI_VIB: >>>> + mask = SPMI_VIB_DRV_LEVEL_MASK; >>>> + shift = SPMI_VIB_DRV_SHIFT; >>>> + break; >>>> + case SPMI_VIB_GEN2: >>>> + mask = SPMI_VIB_GEN2_DRV_MASK; >>>> + shift = SPMI_VIB_GEN2_DRV_SHIFT; >>>> + break; >>>> + default: >>>> + return -EINVAL; >>> Could you please move the switch to the previous patch? Then it would >>> be more obvious that you are just adding the SPMI_VIB_GEN2 here. >>> >>> Other than that LGTM. >> >> Sure, I can move the switch to the previous refactoring patch. > > Actually, the idea of having a const "reg" or "chip", etc. structure is > to avoid this kind of runtime checks based on hardware type and instead > use common computation. I believe you need to move mask and shift into > the chip-specific structure and avoid defining hw_type. > > Thanks. Hi Dmitry, The v7 changes have been pending for a while, I am not sure if you are still insist on this. As I explained, I actually did it this way in v2 and it got updated to this by following other comments. Can you respond and tell me if you prefer changes similar to v2? I can update and push v8 by following your suggestion. v7: https://lore.kernel.org/linux-arm-msm/20231108-pm8xxx-vibrator-v7-0-632c731d25a8@quicinc.com/ v2: https://lore.kernel.org/linux-arm-msm/20230718062639.2339589-3-quic_fenglinw@quicinc.com/ Thanks >