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AJvYcCXtIJth04wx0/tTGnfz96UvCgIgZ7Fd3p86VpZEG/f2JrvnGu6c59BY4IVtaEU92TvqKALfZcn+xuWRPnZpe1T+sV2oPjO9mRlDP1lv X-Gm-Message-State: AOJu0YwQGxNSVZ725TjEaZrBxlPcjoPu/we8kdWVKfQ/EJW1Ua2Fjzjc s0uXwBBDomth8mSxZ53xBLH1Rki4DDZ7jJDG7+Wwi4k8NdPYc/zFMjcFettdvJBxSzlKuy1nfQ/ yUK9Q04ylJ+xNnHhGi7JOoYZ52Gf5xzDSn8RHwQ== X-Received: by 2002:a25:9b85:0:b0:dd0:39a0:a998 with SMTP id v5-20020a259b85000000b00dd039a0a998mr2199704ybo.6.1711617316176; Thu, 28 Mar 2024 02:15:16 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20240313092809.2596644-1-billy_tsai@aspeedtech.com> In-Reply-To: <20240313092809.2596644-1-billy_tsai@aspeedtech.com> From: Linus Walleij Date: Thu, 28 Mar 2024 10:15:05 +0100 Message-ID: Subject: Re: [PATCH v2] pinctrl: pinctrl-aspeed-g6: Fix register offset for pinconf of GPIOR-T To: Billy Tsai Cc: andrew@codeconstruct.com.au, joel@jms.id.au, johnny_huang@aspeedtech.com, linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, BMC-SW@aspeedtech.com, Ricky_CX_Wu@wiwynn.com, Delphine CC Chiu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Mar 13, 2024 at 10:28=E2=80=AFAM Billy Tsai wrote: > The register offset to disable the internal pull-down of GPIOR~T is 0x630 > instead of 0x620, as specified in the Ast2600 datasheet v15 > The datasheet can download from the official Aspeed website. > > Fixes: 15711ba6ff19 ("pinctrl: aspeed-g6: Add AST2600 pinconf support") > Signed-off-by: Billy Tsai Patch applied. I recorded Delphine's similar patch as "reported-by". Yours, Linus Walleij