Received-SPF: pass (google.com: domain of linux-kernel+bounces-123121-linux.lists.archive=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) client-ip=147.75.48.161;
Date: Thu, 28 Mar 2024 10:57:35 -0400
From: Frank Li <Frank.li@nxp.com>
To: Shawn Guo <shawnguo2@yeah.net>
Cc: Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Fabio Estevam <festevam@gmail.com>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@vger.kernel.org>,
	"open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" <imx@lists.linux.dev>,
	"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" <linux-arm-kernel@lists.infradead.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/1] arm64: dts: imx8qxp: add asrc[0,1], esai0,
 spdif[0,1] and sai[4,5]
Message-ID: <ZgWFX70McJc5PoNg@lizhi-Precision-Tower-5810>
References: <20240226192130.259288-1-Frank.Li@nxp.com>
 <ZgV6a7ZMwM4aR7f+@dragon>
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <ZgV6a7ZMwM4aR7f+@dragon>
Precedence: bulk
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0:
	=?us-ascii?Q?a1XRmNBNU+vDia+SgCCqOF0XGhPsnMaUs8jGnq6AfP6SRHnoojxa/23Wn9ld?=
 =?us-ascii?Q?myucYUlhK8bH+qkf2uP3bSN0qBqK9Bs28yjmPtEBg8BFnzq2lW188tZNc39W?=
 =?us-ascii?Q?rt0E3dS+Jl6BWlpUGHxn627siWwPXR35ehsODSH3/jArjsGKf0uHq9MV+cqU?=
 =?us-ascii?Q?M2J8wY9v+pjAuR2LIAZvcBHbrWNic+mB61qEejZwcC2tYg6FJpG9PB2wa9+9?=
 =?us-ascii?Q?HOUolhtVkYGlfDNL4cuNKCgc+1UB2Te/aodeEetCLR1mM2kEH8EdLR78Kdm1?=
 =?us-ascii?Q?9qbEuuW1fik8PR0GEV+nCD/5p3B0+lRwcWx7LfABCqDAqWvxdKPStwIn2hl+?=
 =?us-ascii?Q?NGNsvWy2+ro3GyELnZ0/9oMltdGrlNXdo71AOF9UvWcHHrSdsKdaRwxSVJ7i?=
 =?us-ascii?Q?VntGLDvgeteI8B2x+dLkLPBde05KTQcWg1TFSVogtYxKPTW9eLsyVyhEpFCf?=
 =?us-ascii?Q?ziL0YUWasrKjNaaRF9vYq6qio0AijHWQsctmKMT+17m8U9usRc1ucAH+f8jC?=
 =?us-ascii?Q?c6LAbBtf48f4H8zcMjfRW3srEbYapZj5rKDPN5gK2jMgke/yPpH5VRJNMUTA?=
 =?us-ascii?Q?7cSqk32yJrZX19ABEqMhWzHFDg7LB5Kg7yf6JXxvONVsV0u7sXH11H1LaUS7?=
 =?us-ascii?Q?7BC/Z/CuWwzDZV/+gzfdPUOTpy1wp466fhE0jZrEEZFAtsk4tkVzPS//WG+A?=
 =?us-ascii?Q?ZUsmCFqOqEVfsI+DOxIP403BYvnzggDVJKpovsB9B9c7Jkr5OVnF12Aoo8Jf?=
 =?us-ascii?Q?w0NnWX88SGI1s1gkpOK+sJd+qItXolj0H0psawsRtheYZWHtAdaQLglHlQzS?=
 =?us-ascii?Q?zNETBpn9pCkSmq6/EmkvMwSac0v8tWp+72TFmS6OPq8RCUZcrvNhAqoTzBBE?=
 =?us-ascii?Q?vgaI3mPy3RFzFxgHglY4hCm1YoANi59FzUZWf4agy7ZkzF3NWtDzjKI8vnnn?=
 =?us-ascii?Q?JMiS/hKH4OMzrjJnUdo4aq2kHV33JHMJXJo99S3mFuy0EgYF+AIPnsNh6ba4?=
 =?us-ascii?Q?yfPWxYzWNdF4Pe+AkTATgj2KQsvYlezHBpZ+6LF7ZifU7wCvmgnB/pDCnv2X?=
 =?us-ascii?Q?/YHFPNRLrQdmfz+HYsB7P6JaCCl+KddPZsgTljyDxkXOaueLXL6maANsG5JC?=
 =?us-ascii?Q?rtP9ipb/1/vsrK4fxFWJI5DIgm4sJkszuK8iQ8gy83JU9AHirubuMTDb1/YZ?=
 =?us-ascii?Q?yxskZ8eNAhjiZ2An6nRT7OtRMjabcKr9h13VU3O+ME0zNNm+ege5gqM/w9w6?=
 =?us-ascii?Q?CiI6hTlUdZONqo+tGyFcjaGpBxiwNexzsNXqyrOWFw//HZBMQsMMwF5QzWtj?=
 =?us-ascii?Q?FnqYOEv7/ZLGp5B6rrKirxGpwPeu+OhFd1cKvv46GnloBGUflYwiHEKdne6e?=
 =?us-ascii?Q?RVbYsTuGnCfOiFv9LfH1q+SN+GD8/GbVsn2n4QXi9dofV9wHYbuw5VZTTBau?=
 =?us-ascii?Q?cP0UI4p9q85sFdkbTiWHMsQRN7flvCEeja1B9Hc7ES1wDtnXOewk+7KWSmZq?=
 =?us-ascii?Q?1rJitazF2c2GxSXxUVNQfHVAp6cg3ug/wpgYb5IbnRfWLHJnSs7O96OkjZdG?=
 =?us-ascii?Q?MqZ0tOyV4FBab3RUih7J8XCisXnNl5EkQCXBcpjL?=
X-OriginatorOrg: nxp.com
X-MS-Exchange-CrossTenant-Network-Message-Id: fb717032-b944-4cbc-5987-08dc4f376c13
X-MS-Exchange-CrossTenant-AuthSource: PAXPR04MB9642.eurprd04.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Mar 2024 14:57:43.5567
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: sG7+/KpZhkkBRTbIw67hjiR43N/WHNcFRZ2JseQI/tt09Q4sDcZAsZg44KKRoGsk5HZmndfPVwekSv4b1RHUsw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7916

On Thu, Mar 28, 2024 at 10:10:51PM +0800, Shawn Guo wrote:
> On Mon, Feb 26, 2024 at 02:21:29PM -0500, Frank Li wrote:
> > Add asrc[0,1], esai0, spdif[0,1], sai[4,5] and related lpcg node for
> > imx8 audio subsystem.
> > 
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  .../boot/dts/freescale/imx8-ss-audio.dtsi     | 306 ++++++++++++++++++
> >  1 file changed, 306 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> > index 07afeb78ed564..6d78d6c0d9002 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
> > @@ -6,6 +6,7 @@
> >  
> >  #include <dt-bindings/clock/imx8-clock.h>
> >  #include <dt-bindings/clock/imx8-lpcg.h>
> > +#include <dt-bindings/dma/fsl-edma.h>
> >  #include <dt-bindings/firmware/imx/rsrc.h>
> >  
> >  audio_ipg_clk: clock-audio-ipg {
> > @@ -481,4 +482,309 @@ acm: acm@59e00000 {
> >  			      "sai3_rx_bclk",
> >  			      "sai4_rx_bclk";
> >  	};
> > +
> > +	asrc0: asrc@59000000 {
> 
> We want to sort nodes in unit-address, right?

Actually it is fixed at v2. I just send out v8, which include extra space
fix and wrong clock index fixes.

https://lore.kernel.org/imx/20240328-asrc_8qxp-v8-0-801cd6bb5be2@nxp.com/T/#t

Also need below patches to make board level audio work.
https://lore.kernel.org/imx/20240305-m4_lpuart-v3-0-592463ef1d22@nxp.com/

Frank

> 
> > +		compatible = "fsl,imx8qm-asrc";
> > +		reg = <0x59000000 0x10000>;
> > +		interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
> > +			     <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
> > +		clocks = <&asrc0_lpcg 0>,
> > +			 <&asrc0_lpcg 0>,
> > +			 <&aud_pll_div0_lpcg 0>,
> > +			 <&aud_pll_div1_lpcg 0>,
> > +			 <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
> > +			 <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>;
> > +		clock-names = "ipg", "mem",
> > +			      "asrck_0", "asrck_1", "asrck_2", "asrck_3",
> > +			      "asrck_4", "asrck_5", "asrck_6", "asrck_7",
> > +			      "asrck_8", "asrck_9", "asrck_a", "asrck_b",
> > +			      "asrck_c", "asrck_d", "asrck_e", "asrck_f",
> > +			      "spba";
> > +		dmas = <&edma0 0 0 0>,
> > +		       <&edma0 1 0 0>,
> > +		       <&edma0 2 0 0>,
> > +		       <&edma0 3 0 FSL_EDMA_RX>,
> > +		       <&edma0 4 0 FSL_EDMA_RX>,
> > +		       <&edma0 5 0 FSL_EDMA_RX>;
> > +		/* tx* is output channel of asrc, it is rx channel for eDMA */
> > +		dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
> > +		fsl,asrc-rate  = <8000>;
> 
> One space around =
> 
> > +		fsl,asrc-width = <16>;
> > +		fsl,asrc-clk-map = <0>;
> > +		power-domains = <&pd IMX_SC_R_ASRC_0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	esai0: esai@59010000 {
> > +		compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";
> > +		reg = <0x59010000 0x10000>;
> > +		interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> > +		clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>;
> > +		clock-names = "core", "extal", "fsys", "spba";
> > +		dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>;
> > +		dma-names = "rx", "tx";
> > +		power-domains = <&pd IMX_SC_R_ESAI_0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	spdif0: spdif@59020000 {
> > +		compatible = "fsl,imx8qm-spdif";
> > +		reg = <0x59020000 0x10000>;
> > +		interrupts =  <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, /* rx */
> 
> Ditto
> 
> > +			      <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>; /* tx */
> > +		clocks = <&spdif0_lpcg 1>,	/* core */
> > +			 <&clk_dummy>,		/* rxtx0 */
> > +			 <&spdif0_lpcg 0>,	/* rxtx1 */
> > +			 <&clk_dummy>,		/* rxtx2 */
> > +			 <&clk_dummy>,		/* rxtx3 */
> > +			 <&clk_dummy>,		/* rxtx4 */
> > +			 <&audio_ipg_clk>,	/* rxtx5 */
> > +			 <&clk_dummy>,		/* rxtx6 */
> > +			 <&clk_dummy>,		/* rxtx7 */
> > +			 <&clk_dummy>;		/* spba */
> > +		clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
> > +			      "rxtx5", "rxtx6", "rxtx7", "spba";
> > +		dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
> > +		       <&edma0 9 0 FSL_EDMA_MULTI_FIFO>;
> > +		dma-names = "rx", "tx";
> > +		power-domains = <&pd IMX_SC_R_SPDIF_0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	spdif1: spdif@59030000 {
> > +		compatible = "fsl,imx8qm-spdif";
> > +		reg = <0x59030000 0x10000>;
> > +		interrupts =  <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, /* rx */
> 
> Ditto
> 
> Shawn
> 
> > +			      <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; /* tx */
> > +		clocks = <&spdif1_lpcg 1>,	/* core */
> > +			 <&clk_dummy>,		/* rxtx0 */
> > +			 <&spdif1_lpcg 0>,	/* rxtx1 */
> > +			 <&clk_dummy>,		/* rxtx2 */
> > +			 <&clk_dummy>,		/* rxtx3 */
> > +			 <&clk_dummy>,		/* rxtx4 */
> > +			 <&audio_ipg_clk>,	/* rxtx5 */
> > +			 <&clk_dummy>,		/* rxtx6 */
> > +			 <&clk_dummy>,		/* rxtx7 */
> > +			 <&clk_dummy>;		/* spba */
> > +		clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
> > +			      "rxtx5", "rxtx6", "rxtx7", "spba";
> > +		dmas = <&edma0 10 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
> > +		       <&edma0 11 0 FSL_EDMA_MULTI_FIFO>;
> > +		dma-names = "rx", "tx";
> > +		power-domains = <&pd IMX_SC_R_SPDIF_1>;
> > +		status = "disabled";
> > +	};
> > +
> > +	asrc1: asrc@59800000 {
> > +		compatible = "fsl,imx8qm-asrc";
> > +		reg = <0x59800000 0x10000>;
> > +		interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
> > +			     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
> > +		clocks = <&asrc1_lpcg 0>,
> > +			 <&asrc1_lpcg 0>,
> > +			 <&aud_pll_div0_lpcg 0>,
> > +			 <&aud_pll_div1_lpcg 0>,
> > +			 <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>,
> > +			 <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>;
> > +		clock-names = "ipg", "mem",
> > +			      "asrck_0", "asrck_1", "asrck_2", "asrck_3",
> > +			      "asrck_4", "asrck_5", "asrck_6", "asrck_7",
> > +			      "asrck_8", "asrck_9", "asrck_a", "asrck_b",
> > +			      "asrck_c", "asrck_d", "asrck_e", "asrck_f",
> > +			      "spba";
> > +		dmas = <&edma1 0 0 0>,
> > +		       <&edma1 1 0 0>,
> > +		       <&edma1 2 0 0>,
> > +		       <&edma1 3 0 FSL_EDMA_RX>,
> > +		       <&edma1 4 0 FSL_EDMA_RX>,
> > +		       <&edma1 5 0 FSL_EDMA_RX>;
> > +		/* tx* is output channel of asrc, it is rx channel for eDMA */
> > +		dma-names = "txa", "txb", "txc", "rxa", "rxb", "rxc";
> > +		fsl,asrc-rate  = <8000>;
> > +		fsl,asrc-width = <16>;
> > +		fsl,asrc-clk-map = <1>;
> > +		power-domains = <&pd IMX_SC_R_ASRC_1>;
> > +		status = "disabled";
> > +	};
> > +
> > +	sai4: sai@59820000 {
> > +		compatible = "fsl,imx8qm-sai";
> > +		reg = <0x59820000 0x10000>;
> > +		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
> > +		clocks = <&sai4_lpcg 1>,
> > +			 <&clk_dummy>,
> > +			 <&sai4_lpcg 0>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>;
> > +		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
> > +		dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>;
> > +		dma-names = "rx", "tx";
> > +		power-domains = <&pd IMX_SC_R_SAI_4>;
> > +		status = "disabled";
> > +	};
> > +
> > +	sai5: sai@59830000 {
> > +		compatible = "fsl,imx8qm-sai";
> > +		reg = <0x59830000 0x10000>;
> > +		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
> > +		clocks = <&sai5_lpcg 1>,
> > +			 <&clk_dummy>,
> > +			 <&sai5_lpcg 0>,
> > +			 <&clk_dummy>,
> > +			 <&clk_dummy>;
> > +		clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
> > +		dmas = <&edma1 10 0 0>;
> > +		dma-names = "tx";
> > +		power-domains = <&pd IMX_SC_R_SAI_5>;
> > +		status = "disabled";
> > +	};
> > +
> > +	amix: amix@59840000 {
> > +		compatible = "fsl,imx8qm-audmix";
> > +		reg = <0x59840000 0x10000>;
> > +		clocks = <&amix_lpcg 0>;
> > +		clock-names = "ipg";
> > +		power-domains = <&pd IMX_SC_R_AMIX>;
> > +		dais = <&sai4>, <&sai5>;
> > +		status = "disabled";
> > +	};
> > +
> > +	mqs: mqs@59850000 {
> > +		compatible = "fsl,imx8qm-mqs";
> > +		reg = <0x59850000 0x10000>;
> > +		clocks = <&mqs0_lpcg 1>,
> > +			<&mqs0_lpcg 0>;
> > +		clock-names = "core", "mclk";
> > +		power-domains = <&pd IMX_SC_R_MQS_0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	asrc0_lpcg: clock-controller@59400000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x59400000 0x10000>;
> > +		#clock-cells = <1>;
> > +		clocks = <&audio_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "asrc0_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_ASRC_0>;
> > +	};
> > +
> > +	esai0_lpcg: clock-controller@59410000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x59410000 0x10000>;
> > +		#clock-cells = <1>;
> > +		clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
> > +			 <&audio_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "esai0_lpcg_extal_clk",
> > +				     "esai0_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_ESAI_0>;
> > +	};
> > +
> > +	spdif0_lpcg: clock-controller@59420000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x59420000 0x10000>;
> > +		#clock-cells = <1>;
> > +		clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>,
> > +			 <&audio_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "spdif0_lpcg_tx_clk",
> > +				     "spdif0_lpcg_gclkw";
> > +		power-domains = <&pd IMX_SC_R_SPDIF_0>;
> > +	};
> > +
> > +	spdif1_lpcg: clock-controller@59430000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x59430000 0x10000>;
> > +		#clock-cells = <1>;
> > +		clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>,
> > +			 <&audio_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "spdif1_lpcg_tx_clk",
> > +				     "spdif1_lpcg_gclkw";
> > +		power-domains = <&pd IMX_SC_R_SPDIF_1>;
> > +		status = "disabled";
> > +	};
> > +
> > +	asrc1_lpcg: clock-controller@59c00000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x59c00000 0x10000>;
> > +		#clock-cells = <1>;
> > +		clocks = <&audio_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "asrc1_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_ASRC_1>;
> > +	};
> > +
> > +	sai4_lpcg: clock-controller@59c20000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x59c20000 0x10000>;
> > +		#clock-cells = <1>;
> > +		clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>,
> > +			 <&audio_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "sai4_lpcg_mclk",
> > +				     "sai4_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_SAI_4>;
> > +	};
> > +
> > +	sai5_lpcg: clock-controller@59c30000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x59c30000 0x10000>;
> > +		#clock-cells = <1>;
> > +		clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>,
> > +			 <&audio_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "sai5_lpcg_mclk",
> > +				     "sai5_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_SAI_5>;
> > +	};
> > +
> > +	amix_lpcg: clock-controller@59c40000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x59c40000 0x10000>;
> > +		#clock-cells = <1>;
> > +		clocks = <&audio_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "amix_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_AMIX>;
> > +	};
> > +
> > +	mqs0_lpcg: clock-controller@59c50000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x59c50000 0x10000>;
> > +		#clock-cells = <1>;
> > +		clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>,
> > +			 <&audio_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "mqs0_lpcg_mclk",
> > +				     "mqs0_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MQS_0>;
> > +	};
> >  };
> > -- 
> > 2.34.1
> > 
>