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Thu, 28 Mar 2024 16:08:19 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id BFE3F2248BB; Thu, 28 Mar 2024 16:07:03 +0100 (CET) Received: from [10.201.21.128] (10.201.21.128) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Mar 2024 16:07:02 +0100 Message-ID: <6df41c81-0aa4-48a5-a069-d8a742f412ef@foss.st.com> Date: Thu, 28 Mar 2024 16:07:01 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 1/1] dt-bindings: net: dwmac: Document STM32 property st,ext-phyclk Content-Language: en-US To: Marek Vasut , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown CC: , , , , References: <20240328140803.324141-1-christophe.roullier@foss.st.com> <20240328140803.324141-2-christophe.roullier@foss.st.com> <480d4064-b553-4005-ad98-499a862703ff@denx.de> From: Christophe ROULLIER In-Reply-To: <480d4064-b553-4005-ad98-499a862703ff@denx.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-28_15,2024-03-27_01,2023-05-22_02 On 3/28/24 15:19, Marek Vasut wrote: > On 3/28/24 3:08 PM, Christophe Roullier wrote: > > [...] > >> | RMII    |    -   |     eth-ck    | eth-ck        |       n/a        | >> |         |        | st,ext-phyclk | st,eth-ref-clk-sel >> |                  | >> |         |        |               | or st,ext-phyclk >> |                  | >> >> --------------------------------------------------------------------------- >> >> >> Reviewed-by: Krzysztof Kozlowski >> Signed-off-by: Christophe Roullier >> --- >>   Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 7 +++++++ >>   1 file changed, 7 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml >> b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml >> index fc8c96b08d7dc..b35eae80ed6ac 100644 >> --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml >> +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml >> @@ -82,6 +82,13 @@ properties: >>         Should be phandle/offset pair. The phandle to the syscon node >> which >>         encompases the glue register, and the offset of the control >> register >>   +st,ext-phyclk: > > Don't you need two spaces in front of the 'st,' here ? Sorry, that's right. > >> +    description: >> +      set this property in RMII mode when you have PHY without >> crystal 50MHz and want to >> +      select RCC clock instead of ETH_REF_CLK. OR in RGMII mode when >> you want to select >> +      RCC clock instead of ETH_CLK125. >> +    type: boolean >> + > > With that fixed: > > Reviewed-by: Marek Vasut