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From: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>
To: Caleb Connolly <caleb.connolly@linaro.org>
CC: Konrad Dybcio <konrad.dybcio@linaro.org>,
        Bjorn Andersson
	<andersson@kernel.org>,
        "linux-arm-msm@vger.kernel.org"
	<linux-arm-msm@vger.kernel.org>,
        "linux-kernel@vger.kernel.org"
	<linux-kernel@vger.kernel.org>,
        Douglas Anderson <dianders@chromium.org>,
        Rob
 Clark <robdclark@gmail.com>
Subject: Re: [PATCH] soc: qcom: cmd-db: map shared memory as WT, not WB
Thread-Topic: [PATCH] soc: qcom: cmd-db: map shared memory as WT, not WB
Thread-Index: AQHagIKviCrPH112HEOpsjr5BCtYWLFMDkOAgAAEYgCAAAGHAIAAJ/GAgAFvKoA=
Date: Thu, 28 Mar 2024 21:29:52 +0000
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Hi Caleb,

Caleb Connolly <caleb.connolly@linaro.org> writes:

> On 27/03/2024 21:06, Konrad Dybcio wrote:
>> On 27.03.2024 10:04 PM, Volodymyr Babchuk wrote:
>>>
>>> Hi Konrad,
>>>
>>> Konrad Dybcio <konrad.dybcio@linaro.org> writes:
>>>
>>>> On 27.03.2024 9:09 PM, Volodymyr Babchuk wrote:
>>>>> It appears that hardware does not like cacheable accesses to this
>>>>> region. Trying to access this shared memory region as Normal Memory
>>>>> leads to secure interrupt which causes an endless loop somewhere in
>>>>> Trust Zone.
>>>>>
>>>>> The only reason it is working right now is because Qualcomm Hyperviso=
r
>>>>> maps the same region as Non-Cacheable memory in Stage 2 translation
>>>>> tables. The issue manifests if we want to use another hypervisor (lik=
e
>>>>> Xen or KVM), which does not know anything about those specific
>>>>> mappings. This patch fixes the issue by mapping the shared memory as
>>>>> Write-Through. This removes dependency on correct mappings in Stage 2
>>>>> tables.
>>>>>
>>>>> I tested this on SA8155P with Xen.
>>>>>
>>>>> Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
>>>>> ---
>>>>
>>>> Interesting..
>>>>
>>>> +Doug, Rob have you ever seen this on Chrome? (FYI, Volodymyr, chromeb=
ooks
>>>> ship with no qcom hypervisor)
>>>
>>> Well, maybe I was wrong when called this thing "hypervisor". All I know
>>> that it sits in hyp.mbn partition and all what it does is setup EL2
>>> before switching to EL1 and running UEFI.
>>>
>>> In my experiments I replaced contents of hyp.mbn with U-Boot, which gav=
e
>>> me access to EL2 and I was able to boot Xen and then Linux as Dom0.
>>=20
>> Yeah we're talking about the same thing. I was just curious whether
>> the Chrome folks have heard of it, or whether they have any changes/
>> workarounds for it.
>
> Does Linux ever write to this region? Given that the Chromebooks don't
> seem to have issues with this (we have a bunch of them in pmOS and I'd
> be very very surprised if this was an issue there which nobody had tried
> upstreaming before) I'd guess the significant difference here is between
> booting Linux in EL2 (as Chromebooks do?) vs with Xen.

It does not write, but I assume that direction is irrelevant in this
case. AFAIK, CPU signals memory type to the bus for both reads and
writes, just with different signals: ARCACHE[3:0] and AWCACHE[3:0].

>
> Volodymyr: have you tried booting the kernel directly from U-Boot in
> EL2? Can you confirm if this issues also happens then?

Yes, behavior is exactly the same. It does not work with WB, but work
with WC or WT.

--=20
WBR, Volodymyr=