Received: by 2002:ab2:b82:0:b0:1f3:401:3cfb with SMTP id 2csp867872lqh; Thu, 28 Mar 2024 21:47:05 -0700 (PDT) X-Forwarded-Encrypted: i=3; AJvYcCUPo0C5EmyuPCUQMHbHOi8nyp11847I1rgYGMwaDx/qFhqDMkGMpoJZrqbx+3a9daV+yoiRD8acnuOo1LKGYWmgcPevex37dun+LM3How== X-Google-Smtp-Source: AGHT+IHFBZA1/j2ycCoEhVVss+CeGODbZaRwrPLfO6b4IWbRMhC5DqLJ5AlKyGX0K7/Vzr/1AVGC X-Received: by 2002:a05:622a:1a0e:b0:42e:b936:78b1 with SMTP id f14-20020a05622a1a0e00b0042eb93678b1mr1582224qtb.58.1711687625145; Thu, 28 Mar 2024 21:47:05 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1711687625; cv=pass; d=google.com; s=arc-20160816; b=bv87evK/dIy9BMr74LccBX72lA+tpJzrhZafU7iFcWslHr+BUgHnp/19KsPEGd0U/6 EMj1aZfrozGK7EPZLyYPFfm2On97uLVzE16nopDZeWQhYgHq/OJLR9k2vuhZBZEpm2nw cxm28FoUpk24ecUdlIPzlaJ4ZNpucaiiBgFbgK/rAu0ZXwy3lY6KnxrECnoY2GRPLA/a dJQ6Ue2J1Bdklu1HYqDAtzOWAaOTyHeE22QKmY8jlxw5vABbg1NXRax9P/WQVSi4HvL+ woJTP/KKl9L2oeFyb6P88+Tn+qqBfpVJq8htb0F6TlQ5PkC7xKDKfiFnlvYGCImvb3lg Mqdw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=iaRh0bZD1J49LQcAlor7p4SEY3y50QUlPea61yaZwvU=; fh=4iSt1GvhxdwzsiI5FbJp2SVDlplwkOVW3lNRQzzc3YY=; b=Z5+NIuTsVlUQlIRIKVFIUwgwyp9L1snLii1TLBRmSdWp3UfOXVyVYyHETM9g5yQwUN y1p9RMI2vLmHIXaUqZdk6HtinDkhlWtSbZPz9SVYtosRf8x0+j1cPBNVXsOPaND1VBj9 NYfkyJPPmxZGI1d9uNMQ0nbAmf2D0B97E/TCJfjCcLiXHqqFSN5qEmzQIe/iF91BRzvR PViTkqKld2YZW9c32J787gIu6s0eDAzt3AGBbXEdWrQIWgaRllxfcQYG0ghZpPy80tjn HLzLqFPFfB3UI5Y7DpxrRiTugPi6nkGZaTQf1i43tIf8C7Aw+HWj2xIa2emfgcI1ggBn +PyQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=TwzepebZ; arc=pass (i=1 spf=pass spfdomain=rivosinc.com dkim=pass dkdomain=rivosinc-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-124123-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-124123-linux.lists.archive=gmail.com@vger.kernel.org" Return-Path: Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id t32-20020a05622a182000b0042ea9d4f6cbsi2975452qtc.527.2024.03.28.21.47.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 21:47:05 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel+bounces-124123-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=TwzepebZ; arc=pass (i=1 spf=pass spfdomain=rivosinc.com dkim=pass dkdomain=rivosinc-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-124123-linux.lists.archive=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-124123-linux.lists.archive=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id C9FBB1C21EF4 for ; Fri, 29 Mar 2024 04:47:04 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4A1343B2BE; Fri, 29 Mar 2024 04:46:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="TwzepebZ" Received: from mail-oa1-f54.google.com (mail-oa1-f54.google.com [209.85.160.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44B4F3D38E for ; Fri, 29 Mar 2024 04:46:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.160.54 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711687571; cv=none; b=ulHIy8CTlBEGttXWMvQf0CCp3lmFbgkc1QLujHHa7jbSEe6qlzC3JudMtZzy+m9Iz5+fGajqpY+U4BuWJVe7tNFIL8neGRBYGkBQ/+Blo1iG/oH0EiOVj+6wV6cBDQqwc8c4xtRNZ2AWilHlVUOJZbUg00597ghD1vKThPkTmnE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711687571; c=relaxed/simple; bh=IW143xJURtg+Eysh7Im4AL2BLTYlddQmWbxTpQHY3lk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nGKg4WiiQgawoWyxqHTvS2d4zrtmbtDOA41hqB1G1VFl+jfOpk0WWKqifciZS0pG8lpFZD7pSEXju8o8sJ4xBmjVDX+O7w0ew7eOe26roDxac2o+JmDr5dXrx6VSY7w0vfB75/s3eoLUOAAOm2GmguvRYxOdbI0VKNLL/UqtxM8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=TwzepebZ; arc=none smtp.client-ip=209.85.160.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-oa1-f54.google.com with SMTP id 586e51a60fabf-229b2396180so1019329fac.0 for ; Thu, 28 Mar 2024 21:46:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1711687567; x=1712292367; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iaRh0bZD1J49LQcAlor7p4SEY3y50QUlPea61yaZwvU=; b=TwzepebZS2Gshs7tluoWzup69tHFkVbK65wWjHo7/aBPCXAqE7/K05zxnEnxj73APa imvuQAestXWEbIl8xgI3aiB005qAd4mklYiHlZvPLRLY2l07RozhIJjlTUxftSdcnRhL 9tO7svzXgAi0dgnzbkZtzkrcfJt39E4MNLOPzxpccj9cyX/n6gAYy4CiwHIWfaJSM52V LBQeL8t4DvjCXMF7qDR5ge5jkeeI+zPt7oRg8iahu2gi9kilJ4gjcd9Tf/jnO/7+IUNr R3Rlc4DXnSO87BcT7jHdRty3RySp6+hRvq4SonQ4VTRGULa9Cs55bmwXkRhGJrir0ycU 2avg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1711687567; x=1712292367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iaRh0bZD1J49LQcAlor7p4SEY3y50QUlPea61yaZwvU=; b=Z089Ix390ZvLTLeWCPuIx2Rc1EhBAg9AlXTYiSiYqmX41w5FTFHC0qnztv0q1GGEUf jJ02q0sgjYT+ndefvdPtWptzzIU+HDDTnzSqcRZ6wzkM4A0qyIKLroe0Jtof9C09b7/U jqylW0oe7BujMmdRBvsXm3JXRd6O61EnL+nG7ebzyYUC4sL37Ay8RyTI3hmBgRiM/AvF S1MheT3vj4I+Vup9KUZaKifCabTwFWFS/gzxjkd2rIUudDxpd2RzYmHXbLtVkzP1mVto CjtseWGFomt00p6HUDJp4l7aHOV4XKqyiGAZmuWkBcW/pgx4SBzOvCtwcbzS2uToXFFl aM8g== X-Forwarded-Encrypted: i=1; AJvYcCWnLad7kF1KRYMDuu3SxY3+rTawv/gySii8258fdU1oe8EN7wpANA8NXdhAGRDgcxFPDYWxK3nDkt8dFrVmWzZACAwTtyfkj4Tza/AV X-Gm-Message-State: AOJu0YzcnRoHdRoSts2crhgtEQMnxBYzqz0fVYYrgosra8I9e75O6YOd N8EmfpJs9PkFi6KzBYhpaPB2TMLyaiLgCGjUzQ/egPMMWLpnwmMnKu3dkZIkqbA= X-Received: by 2002:a05:6870:96a4:b0:22a:5f92:96fd with SMTP id o36-20020a05687096a400b0022a5f9296fdmr1377784oaq.25.1711687567318; Thu, 28 Mar 2024 21:46:07 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id i18-20020aa78b52000000b006ea7e972947sm2217120pfd.130.2024.03.28.21.46.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Mar 2024 21:46:07 -0700 (PDT) From: Deepak Gupta To: paul.walmsley@sifive.com, rick.p.edgecombe@intel.com, broonie@kernel.org, Szabolcs.Nagy@arm.com, kito.cheng@sifive.com, keescook@chromium.org, ajones@ventanamicro.com, conor.dooley@microchip.com, cleger@rivosinc.com, atishp@atishpatra.org, alex@ghiti.fr, bjorn@rivosinc.com, alexghiti@rivosinc.com, samuel.holland@sifive.com, palmer@sifive.com, conor@kernel.org, linux-doc@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-kselftest@vger.kernel.org Cc: corbet@lwn.net, tech-j-ext@lists.risc-v.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, oleg@redhat.com, akpm@linux-foundation.org, arnd@arndb.de, ebiederm@xmission.com, Liam.Howlett@oracle.com, vbabka@suse.cz, lstoakes@gmail.com, shuah@kernel.org, brauner@kernel.org, debug@rivosinc.com, andy.chiu@sifive.com, jerry.shih@sifive.com, hankuan.chen@sifive.com, greentime.hu@sifive.com, evan@rivosinc.com, xiao.w.wang@intel.com, charlie@rivosinc.com, apatel@ventanamicro.com, mchitale@ventanamicro.com, dbarboza@ventanamicro.com, sameo@rivosinc.com, shikemeng@huaweicloud.com, willy@infradead.org, vincent.chen@sifive.com, guoren@kernel.org, samitolvanen@google.com, songshuaishuai@tinylab.org, gerg@kernel.org, heiko@sntech.de, bhe@redhat.com, jeeheng.sia@starfivetech.com, cyy@cyyself.name, maskray@google.com, ancientmodern4@gmail.com, mathis.salmen@matsal.de, cuiyunhui@bytedance.com, bgray@linux.ibm.com, mpe@ellerman.id.au, baruch@tkos.co.il, alx@kernel.org, david@redhat.com, catalin.marinas@arm.com, revest@chromium.org, josh@joshtriplett.org, shr@devkernel.io, deller@gmx.de, omosnace@redhat.com, ojeda@kernel.org, jhubbard@nvidia.com Subject: [PATCH v2 06/27] riscv: usercfi state for task and save/restore of CSR_SSP on trap entry/exit Date: Thu, 28 Mar 2024 21:44:38 -0700 Message-Id: <20240329044459.3990638-7-debug@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240329044459.3990638-1-debug@rivosinc.com> References: <20240329044459.3990638-1-debug@rivosinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Carves out space in arch specific thread struct for cfi status and shadow stack in usermode on riscv. This patch does following - defines a new structure cfi_status with status bit for cfi feature - defines shadow stack pointer, base and size in cfi_status structure - defines offsets to new member fields in thread in asm-offsets.c - Saves and restore shadow stack pointer on trap entry (U --> S) and exit (S --> U) Shadow stack save/restore is gated on feature availiblity and implemented using alternative. CSR can be context switched in in `switch_to` as well but soon as kernel shadow stack support gets rolled in, shadow stack pointer will need to be switched at trap entry/exit point (much like `sp`). It can be argued that kernel using shadow stack deployment scenario may not be as prevalant as user mode using this feature. But even if there is some minimal deployment of kernel shadow stack, that means that it needs to be supported. And thus save/restore of shadow stack pointer in entry.S instead of in `switch_to.h`. Signed-off-by: Deepak Gupta --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/include/asm/thread_info.h | 3 +++ arch/riscv/include/asm/usercfi.h | 24 ++++++++++++++++++++++++ arch/riscv/kernel/asm-offsets.c | 4 ++++ arch/riscv/kernel/entry.S | 26 ++++++++++++++++++++++++++ 5 files changed, 58 insertions(+) create mode 100644 arch/riscv/include/asm/usercfi.h diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 6c5b3d928b12..f8decf357804 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -14,6 +14,7 @@ #include #include +#include #ifdef CONFIG_64BIT #define DEFAULT_MAP_WINDOW (UL(1) << (MMAP_VA_BITS - 1)) diff --git a/arch/riscv/include/asm/thread_info.h b/arch/riscv/include/asm/thread_info.h index a503bdc2f6dd..f1dee307806e 100644 --- a/arch/riscv/include/asm/thread_info.h +++ b/arch/riscv/include/asm/thread_info.h @@ -57,6 +57,9 @@ struct thread_info { int cpu; unsigned long syscall_work; /* SYSCALL_WORK_ flags */ unsigned long envcfg; +#ifdef CONFIG_RISCV_USER_CFI + struct cfi_status user_cfi_state; +#endif #ifdef CONFIG_SHADOW_CALL_STACK void *scs_base; void *scs_sp; diff --git a/arch/riscv/include/asm/usercfi.h b/arch/riscv/include/asm/usercfi.h new file mode 100644 index 000000000000..4fa201b4fc4e --- /dev/null +++ b/arch/riscv/include/asm/usercfi.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright (C) 2024 Rivos, Inc. + * Deepak Gupta + */ +#ifndef _ASM_RISCV_USERCFI_H +#define _ASM_RISCV_USERCFI_H + +#ifndef __ASSEMBLY__ +#include + +#ifdef CONFIG_RISCV_USER_CFI +struct cfi_status { + unsigned long ubcfi_en : 1; /* Enable for backward cfi. */ + unsigned long rsvd : ((sizeof(unsigned long)*8) - 1); + unsigned long user_shdw_stk; /* Current user shadow stack pointer */ + unsigned long shdw_stk_base; /* Base address of shadow stack */ + unsigned long shdw_stk_size; /* size of shadow stack */ +}; + +#endif /* CONFIG_RISCV_USER_CFI */ + +#endif /* __ASSEMBLY__ */ + +#endif /* _ASM_RISCV_USERCFI_H */ diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index a03129f40c46..5c5ea015c776 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -44,6 +44,10 @@ void asm_offsets(void) #endif OFFSET(TASK_TI_CPU_NUM, task_struct, thread_info.cpu); +#ifdef CONFIG_RISCV_USER_CFI + OFFSET(TASK_TI_CFI_STATUS, task_struct, thread_info.user_cfi_state); + OFFSET(TASK_TI_USER_SSP, task_struct, thread_info.user_cfi_state.user_shdw_stk); +#endif OFFSET(TASK_THREAD_F0, task_struct, thread.fstate.f[0]); OFFSET(TASK_THREAD_F1, task_struct, thread.fstate.f[1]); OFFSET(TASK_THREAD_F2, task_struct, thread.fstate.f[2]); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 9d1a305d5508..7245a0ea25c1 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -60,6 +60,20 @@ SYM_CODE_START(handle_exception) REG_L s0, TASK_TI_USER_SP(tp) csrrc s1, CSR_STATUS, t0 + /* + * If previous mode was U, capture shadow stack pointer and save it away + * Zero CSR_SSP at the same time for sanitization. + */ + ALTERNATIVE("nop; nop; nop; nop", + __stringify( \ + andi s2, s1, SR_SPP; \ + bnez s2, skip_ssp_save; \ + csrrw s2, CSR_SSP, x0; \ + REG_S s2, TASK_TI_USER_SSP(tp); \ + skip_ssp_save:), + 0, + RISCV_ISA_EXT_ZICFISS, + CONFIG_RISCV_USER_CFI) csrr s2, CSR_EPC csrr s3, CSR_TVAL csrr s4, CSR_CAUSE @@ -141,6 +155,18 @@ SYM_CODE_START_NOALIGN(ret_from_exception) * structures again. */ csrw CSR_SCRATCH, tp + + /* + * Going back to U mode, restore shadow stack pointer + */ + ALTERNATIVE("nop; nop", + __stringify( \ + REG_L s3, TASK_TI_USER_SSP(tp); \ + csrw CSR_SSP, s3), + 0, + RISCV_ISA_EXT_ZICFISS, + CONFIG_RISCV_USER_CFI) + 1: #ifdef CONFIG_RISCV_ISA_V_PREEMPTIVE move a0, sp -- 2.43.2