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Date: Fri, 29 Mar 2024 07:24:57 +0000
From: Conor Dooley <conor.dooley@microchip.com>
To: Deepak Gupta <debug@rivosinc.com>
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Subject: Re: [PATCH v2 04/27] riscv: zicfiss/zicfilp enumeration
Message-ID: <20240329-condition-morse-c3d02720853a@wendy>
References: <20240329044459.3990638-1-debug@rivosinc.com>
 <20240329044459.3990638-5-debug@rivosinc.com>
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On Thu, Mar 28, 2024 at 09:44:36PM -0700, Deepak Gupta wrote:
> Adds description in dt-bindings (extensions.yaml)
>=20
> This patch adds support for detecting zicfiss and zicfilp. zicfiss and zi=
cfilp
> stands for unprivleged integer spec extension for shadow stack and branch
> tracking on indirect branches, respectively.
>=20
> This patch looks for zicfiss and zicfilp in device tree and accordinlgy l=
ights
> up bit in cpu feature bitmap. Furthermore this patch adds detection utili=
ty
> functions to return whether shadow stack or landing pads are supported by
> cpu.
>=20
> Signed-off-by: Deepak Gupta <debug@rivosinc.com>
> ---

>  .../devicetree/bindings/riscv/extensions.yaml       | 10 ++++++++++

Checkpatch should have told you that bindings changes need to be in
separate patches.

Thanks,
Conor.

>  arch/riscv/include/asm/cpufeature.h                 | 13 +++++++++++++
>  arch/riscv/include/asm/hwcap.h                      |  2 ++
>  arch/riscv/include/asm/processor.h                  |  1 +
>  arch/riscv/kernel/cpufeature.c                      |  2 ++

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